RTS CS9500, Руководство пользователя

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Clock and Timing
4.2.2
4.3
4.3.1
The timing
chain starts with a
MHz
clock oscillator module.
The 40 MHz output
is
fed directly to the The
divides the
40
MHz to
2
MHz in order to generate the and
signals for and the CODECS.
This
is the data
The further divides the signal to in order to generate
the Frame-Sync input to the and CODECS.
TROUBLESHOOTING THE SECTION
Check the power supply.
Check the MHz oscillator output and the divided-down clock
signals
to see that they are OK.
Unlike TTL, the CMOS logic ICs used in the Telos One Hybrid
should have a nice almost rail-to-rail
output.
Make sure that all of the required signals are getting to the
CODECS and that the CODECS are
outputting data.
None of the logic section ICs should get hot,
if
any
is,
you've
found the problem. On rare occasions, a chip
may
latch up
and get hot, but recover and work normally when power
is
removed
for awhile
and
restored.
Check the 16 data bus lines to
see if
any are shorted. They should
exhibit lots of activity, as should the lower address bits.
AUDIO SECTION
THEORY OF OPERATION
(Refer to the Block Diagram and the audio section schematic in
the DRAWINGS section of this
manual.)
The audio section is simple and straightforward. Everything
should be self-evident from the schematic.
TECHNICAL TROUBLESHOOTING
27