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73
DMx820 User’s Manual
Bit
Description
Read Write
Value
after
Reset
Value
to Use
22:0
Transfer Size (Bytes).
Indicates the number
of bytes to transfer during a DMA operation.
Yes
Yes
0h
x
30:23
Reserved
Yes
No
0h
0h
31
Ring Management Valid.
When Ring
Management Valid Mode is enabled
(DMAMODE0[20]=1), indicates the validity of
this DMA descriptor.
Yes
Yes
0
x
DMAPRn
DMA Channel n Descriptor Pointer
Bit
Description
Read Write
Value
after
Reset
Value
to Use
0
Descriptor Location.
Writing 1 indicates PCI
Address space. Writing 0 indicates Local
Address space.
Yes
Yes
0h
1
1
End of Chain.
Writing 1 indicates end of
chain. Writing 0 indicates not end of chain
descriptor. (Same as DMA Block mode.)
Yes
Yes
0h
x
2
Interrupt after Terminal Count.
Writing 1
causes an interrupt to be asserted after the
terminal count for this descriptor is reached.
Writing 0 disables interrupts from being
asserted.
Yes
Yes
0h
x
3
Direction of Transfer.
Writing 1 indicates
transfers from the Local Bus to the PCI Bus.
Writing 0 indicates transfers from the PCI Bus
to the Local Bus.
Yes
Yes
0h
x
31:4
Next Descriptor Address.
X0h-aligned
(DMADPR0[3:0]=0h).
Yes
Yes
0h
x
DMACSRn
DMA Channel n Command/Status
Bit
Description
Read Write
Value
after
Reset
Value
to Use
0
Enable.
Writing 1 enables the channel to
transfer data. Writing 0 disables the channel
from starting a DMA transfer, and if in the
process of transferring data, suspends the
transfer (pause).
Yes
Yes
0h
1
1
Start.
Writing 1 causes the channel to start
transferring data if the channel is enabled.
Yes
Yes/
Set
0h
x