RTD Embedded Technologies, Inc.
|
www.rtd.com
60
DMx820 User’s Manual
Field
Description
ENA
Enables or disabled the PWM.
’0’ = Disabled
’1’ = Enabled
PWMn_CLK
This register selects the clock sources for the period and width of the PWM output.
15
8
7
4
3
0
Reserved
PER_CLK[3:0]
WIDTH_CLK[3:0]
R,+0
RW,+0
RW,+0
Field
Description
PER_CLK [3:0]
Selects the master clock for the period counter. Value
definitions are:
15 Inverted Strobe2
14 Inverted Strobe1
13 Strobe2
12 Strobe1
11 Prog. Clock 3
10 Prog. Clock 2
9 Prog. Clock 1
8 Prog. Clock 0
7 82C54 TC B2
6 82C54 TC B1
5 82C54 TC B0
4 82C54 TC A2
3 82C54 TC A1
2 82C54 TC A0
1 Reserved
0 25 MHz
WIDTH_CLK[3:0]
Selects the master clock for the width counter. See above
for value definitions.
PWMn_PERIOD
Sets the maximum width of the PWM outputs. If the period clock and width clock are the same (PWMn_CLK[PER_CLK] =
PWMn_CLK[WIDTH_CLK]), this will also set the PWM period. See Figure 13 on page 59 for more details.
15
0
PERIOD[15:0]
RW,+0
Field
Description
PERIOD[15:0]
The period of the output is the next period clock after:
Frequency
Clock
Width
PERIOD
_
_
)
1
(
PWMn_WIDTHx
Sets the width of output x of the pulse width modulator. The width is based on the clock selected in PWMn_CLK[WIDTH_CLK]. The width is
defined as the time that the non-inverted output is high, and the inverted output is low.
The width register is checked at the beginning of every period. If the width register is modified in the middle of a period, the output will not be
affected until the next period.
Note that with PWMn_PERIOD set to the maximum value, and the period clock and width clock set to the same source, a 100% duty cycle is
not possible.
15
0