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72

DMx820 User’s Manual

18

DAC Chain Load.

When set to 1, enables the

descriptor to load the PCI Dual Address Cycles value.
Otherwise, the descriptor loads the DMADAC0 register
contents.

Yes

Yes

0

x

19

EOT# End Link.

Used only for DMA Scatter/Gather

transfers. Value of 1 indicates that when EOT# is
asserted, the DMA transfer ends the current
Scatter/Gather link and continues with the remaining
Scatter/Gather transfers. Value of 0 indicates that when
EOT# is asserted, the DMA transfer ends the current
Scatter/Gather transfer and does not continue with the
remaining Scatter/Gather transfers.

Yes

Yes

0

0

20

Ring Management Valid Mode Enable.

Value of 0

indicates the Ring Management Valid bit (DMASIZ0[31])
is ignored. Value of 1 indicates the DMA descriptors are
processed only when the Ring Management Valid bit is
set (DMASIZ0[31]=1). If the Valid bit is set, the transfer
count is 0, and the descriptor is not the last descriptor in
the chain. The DMA Controller then moves to the next
descriptor in the chain.

Note:

Descriptor Memory fields are re-ordered when this

bit is set.

Yes

Yes

0

x

21

Ring Management Valid Stop Control.

Value of 0

indicates the DMA Scatter/Gather controller
continuously polls a descriptor with the Valid bit set to 0
(invalid descriptor) if Ring Management Valid Mode is
enabled (DMAMODE0[20]=1).  Value of 1 indicates the
Scatter/Gather controller stops polling when the Ring
Management Valid bit with a value of 0 is detected
(DMASIZ0[31]=0).  In this case, the CPU must restart
the DMA Controller by setting the Start bit
(DMACSR0[1]=1).  A pause clearing the Start bit
(DMACSR0[1]=0) sets the DMA Done bit
(DMACSR0[4]=1).

Yes

Yes

0

x

31:22

Reserved

Yes

No

0

0

DMAPADRn

DMA PCI Address

Bit

Description

Read Write

Value

after

Reset

Value

to Use

31:0

PCI Address.

Indicates from where in PCI

Memory space

DMA transfers (reads or writes) start.

Value is a physical address.

Yes

Yes

0h

x

DMALAPADRn

DMA Local Address

Bit

Description

Read Write

Value

after

Reset

Value

to Use

31:0

DMA Channel Local Address.

Indicates from

where in Local Memory space DMA transfers
(reads or writes) start.

Yes

Yes

0h

x

DMASIZn

DMA Transfer Size

«
...
70
71
72
73
74
...
»

Содержание DM35820HR

Страница 1: ...RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified DM35820HR DM9820HR DM8820HR DM7820HR Versatile High Speed Digital I O User s Manual BDM 610010036 Rev E...

Страница 2: ...RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com...

Страница 3: ...ces multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real...

Страница 4: ...CN10 Digital Input Output 13 Connector CN11 Digital Input Output 14 3 3 3 Bus Connectors 15 PC 104 Express Bus Connectors DM9820HR Only 15 PC 104 Plus PCI Connector 15 PC 104 ISA Connectors DM7820HR O...

Страница 5: ...48 FIFOn_CON_STAT 48 FIFOn_RW_PORT 49 6 3 5 Programmable Clock n 49 PROGCLKn_ID 49 PROGCLKn_MODE 49 PRGCLKn_CLK 50 PRGCLKn_START_STOP 50 PROGCLKn_PERIOD 52 PROGCLKn_COUNT 52 6 3 6 Advanced Interrupt n...

Страница 6: ...Rn 72 DMASIZn 72 DMAPRn 73 DMACSRn 73 DMAARB 74 DMATHR 74 DMADAn 76 INTCSR 76 7 Troubleshooting 79 8 Additional Information 80 PC 104 Specifications 80 PCI and PCI Express Specification 80 PLX PCI9056...

Страница 7: ...3 Counter latching executed for counter 1 Read Load 2 byte setting 67 Table of Tables Table 1 Ordering Options 9 Table 2 Operating Conditions 10 Table 3 Electrical Characteristics 10 Table 4 CN10 Pin...

Страница 8: ...outputs o Single ended or Differential Outputs o 16 bit resolution o Separate period and width clocks provide full resolution at low duty cycles o Optional Interrupt generations Incremental Encoders o...

Страница 9: ...eed Digital I O DAQ Module in IDAN enclosure The Intelligent Data Acquisition Node IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but...

Страница 10: ...t Leakage 0 VI VIO 10 10 uA IOZ PCI Hi Z Leakage 0 VI VIO 10 uA VOH Output High Voltage 2 97 V VOL Output Low Voltage 0 33 V PCIe Bus Differential Output Voltage 0 8 1 2 V DC Differential TX Impedance...

Страница 11: ...eady to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grou...

Страница 12: ...d DM8820HR The DM7820HR and DM8820HR are identical except that the DM8820HR does not have the PC 104 ISA connector populated For a description of each jumper and connector refer to the following secti...

Страница 13: ...CONNECTORS NOTE Pin 1 can be identified by a square solder pad Pins 2 50 have round solder pads Connector CN10 Digital Input Output Connector CN10 provides 24 digital input output lines along with a...

Страница 14: ...Digital Input Output Connector CN11 provides 24 digital input output lines along with a 5V pin and ground pins The pin assignments for CN11 are shown in Table 2 Table 5 CN11 Pin Assignments Signal Pin...

Страница 15: ...the position of the board in the stack Slot 0 represents the PCI device closest to the CPU Slot 3 represents the PCI devices farthest away from the CPU NOTE In a PC 104 Plus or PCI 104 system all PCI...

Страница 16: ...sitions 0 3 will be identical to positions 4 7 NOTE The DM7820HR comes with solder blob B1 open by default This should be compatible with most PC 104 Plus CPUs There is no need to change this blob unl...

Страница 17: ...positioned 10 Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule 11 Hold the module by its edges and orient it so the bus connector pins...

Страница 18: ...the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workbench for testing and handling of your hardwar...

Страница 19: ...5 17 48 GND 18 48 GND 18 7 P0 14 19 7 P1 14 19 28 GND 20 28 GND 20 49 P0 13 21 49 P1 13 21 8 GND 22 8 GND 22 29 P0 12 23 29 P1 12 23 50 GND 24 50 GND 24 9 P0 11 25 9 P1 11 25 30 GND 26 30 GND 26 51 P0...

Страница 20: ...al Characteristics Weight Approximately 0 21 Kg 0 46 lbs Dimensions 151 972 mm L x 129 978 mm W x 16 993 mm H 5 983 in L x 5 117 in W x 0 669 in H Figure 6 IDAN Dimensions 5 117 1 339 5 983 68 pin Fem...

Страница 21: ...18 19 P0 14 19 19 P1 14 19 20 GND 20 20 GND 20 21 P0 13 21 21 P1 13 21 22 GND 22 22 GND 22 23 P0 12 23 23 P1 12 23 24 GND 24 24 GND 24 25 P0 11 25 25 P1 11 25 26 GND 26 26 GND 26 27 P0 10 27 27 P1 10...

Страница 22: ...ignals of the PC 104 Plus PCI bus Refer to PC 104 PlusTM Specification for the pinout of this connector The DM9820HR connects to the power and ground pins only and does not use any of the signals The...

Страница 23: ...pheral cards are connected to the cpuModule 6 Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack 7 Gently and evenly press the module...

Страница 24: ...lock Diagram Below is a block diagram of the DMx820HR Primary board components are in bold while external I O connections and jumpers are italicized Figure 8 DMx820HR Block Diagram PLX PCI9056 or PEX8...

Страница 25: ...e output buffer All of the internal data movement is handled automatically Greatest data efficiency is achieved when there are at least 128 words of data in the FIFO The FIFO also provides Write Reque...

Страница 26: ...mbined to generate a broad range of complex sampling scenarios The following example shows how to use the Advanced Interrupt and 4 counters to capture N words before and M words after an event Program...

Страница 27: ...ne shot 4 Prog Clock 2 Sample output clock a Period same as Prog Clock 0 b Master Clock same as Prog Clock 0 c Start Event Prog Clock 1 d Stop Event AdvInt 0 e Continuous 5 Prog Clock 3 Post Capture c...

Страница 28: ...rs are 16 bits wide However they can be read and written as 8 16 or 32 bits There are a few exceptions as noted in the memory map 6 2 1 MEMORY MAP OVERVIEW Table 9 shows the memory map of the DMx820HR...

Страница 29: ...put 0 for input 0x004E PORT1_MODE b 15 0 1 for peripheral output 0 for digital I O 0x0050 PORT2_OUTPUT b 15 0 Value to port 2 when it is an output 0x0052 PORT2_INPUT b 15 0 Read only value from Port 2...

Страница 30: ...Gate Select 31 16 Port 2 15 0 15 2 Clock_Bus 15 2 1 1 0 0 b 7 4 Reserved b 3 0 Clock Select 15 2 Clock_Bus 15 2 1 reserved 0 5 MHz 0x0086 TC_A1_CONTROL 0x0088 TC_A2_CONTROL 0x008A TC_B0_CONTROL 0x008C...

Страница 31: ...0 ID Register 0x2011 0x00D2 FIFO1_INT b 15 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear b 7 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 7 Reserv...

Страница 32: ...12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0108 PRGCLK0_PERIOD b 1...

Страница 33: ...o Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0188 PRGCLK2_PERIOD b 15 0 Period of Clock Output frequency is 1 _ _ _ _ PERIOD CLK PRG...

Страница 34: ...t on match 0x0216 Reserved 0x0218 ADVINT0_PORT0_CAPT b 15 0 Port 0 Capture Value on Port 0 is written to this register when an interrupt occurs 0x021A ADVINT0_PORT1_CAPT b 15 0 Port 1 Capture Value on...

Страница 35: ..._CLOCK b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 0x0286 INCENC0_MODE b 15 8 Phase Filter Writing a 1 to a specific bit masks out a phase transition b 7 6 Reserved b 5 Differential Mode 1 Pseudo di...

Страница 36: ...nable PWM 0 Disable PWM 0x0304 PWM0_CLK b 7 4 Period Clock Source 15 0 Clock_Bus 15 0 b 3 0 Width Clock Source 15 0 Clock_Bus 15 0 0x0306 Reserved 0x0308 PWM0_PERIOD b 15 0 Period of PWM Cycle is 1 _...

Страница 37: ...d by a register table The first row of the table lists the bits D15 through D0 The second row lists the field name for each bit The third row lists the properties of that bit R bit can be read W bit c...

Страница 38: ...eld Description MSTR Indicates if the board is PCI master capable based on the rotary switch and jumper settings 0 PCI Master 1 Not PCI Master INT_ENABLE This register controls which interrupt sources...

Страница 39: ...Interrupt Disabled 1 Interrupt Enabled FIFO1 Interrupt from FIFO block at 0x00D0 0 Interrupt Disabled 1 Interrupt Enabled INT_STATUS This register shows if any of the interrupt conditions has occurre...

Страница 40: ...Programmable Clock block at 0x0140 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear PClk2 Interrupt from Programmable Clock block at 0x0180 0 Interrupt has not occurred 1 Interr...

Страница 41: ...12 11 10 9 8 Px_15 Px_14 Px_13 Px_12 Px_11 Px_10 Px_9 Px_8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field...

Страница 42: ...10 Px_9 Px_8 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0 Px_7 Px_6 Px_5 Px_4 Px_3 Px_2 Px_1 Px_0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Field Description Px_ 15 0 Port Mode 0 Standard I O...

Страница 43: ...t 8 Port1 9 FIFO0_Out 9 FIFO1_Out 9 Port1 10 FIFO0_Out 10 FIFO1_Out 10 Port1 11 FIFO0_Out 11 FIFO1_Out 11 Port1 12 FIFO0_Out 12 FIFO1_Out 12 Port1 13 FIFO0_Out 13 FIFO1_Out 13 Port1 14 FIFO0_Out 14 FI...

Страница 44: ...1 Output 6 3 3 82C54 TIMER COUNTER CONTROL The Timer Counter Control section is used to select the clock gates and interrupt sources for the 82C54 Timer Counters The actual Timer Counter registers ar...

Страница 45: ...TE_SEL 4 0 Reserved CLOCK_SEL 3 0 R 00 RW 0 R 00 RW 0 Field Description GATE_SEL 4 0 Selects the gate input to this channel of the Timer Counter Value definitions are 31 Port2 15 16 Port2 0 15 Inverte...

Страница 46: ...derflow occurs when the FIFO is empty and the output clock toggles or when the FIFO is read from too fast When the FIFO is disabled the Full Empty and both requests are asserted 15 8 7 0 INT_STAT 7 0...

Страница 47: ...the output clock to the FIFO At every positive edge of the output clock a new word available at the FIFO output 15 5 4 0 Reserved CLOCK_SEL 4 0 R 0 RW 0 Field Description CLOCK_SEL 4 0 Selects the in...

Страница 48: ...te when the FIFO is disabled The DMA engine should only be enabled after the FIFO is enabled FIFOn_CON_STAT ENA 15 10 9 8 7 2 1 0 Reserved DREQ_SRC 1 0 Reserved IN_DATA 1 0 R 0 RW 0 R 0 RW 0 Field Des...

Страница 49: ...data out of the FIFO Writes to this register can be programmed to write data into the FIFO Accesses to this register must be word 16 bit or larger 15 0 DATA 15 0 RW 0 Field Description DATA The read...

Страница 50: ...CK_SEL 3 0 R 0 RW 0 Field Description CLOCK_SEL 3 0 Selects the master clock Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 9 Prog...

Страница 51: ...Interrupt 25 PWM1 Interrupt 24 PWM0 Interrupt 23 Reserved 22 Reserved 21 Incremental Encoder 1 Interrupt 20 Incremental Encoder 0 Interrupt 19 Reserved 18 82C54 Interrupt 17 Advanced Interrupt 1 Inte...

Страница 52: ...rupt 1 Interrupt 16 Advanced Interrupt 0 Interrupt 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 12 Strobe1 11 Prog Clock 3 10 Prog Clock 2 9 Prog Clock 1 8 Prog Clock 0 7 82C54 TC B2 6 82C54 TC...

Страница 53: ...ent PORTx y xor ADVINTn_PORTx_CAPT y and not ADVINTn_PORTx_MASK y 1 ADVINTn_ID ID register to identify an Advanced Interrupt Block 15 0 ID_Register R Field Description ID_Register15 0 Value of 0x0001...

Страница 54: ...mask Bit definitions are 0 Bit is used for match event 1 Bit is ignored ADVINTn_PORTx_CMP The compare register is used for the Match interrupt When all selected bits in this register match all selecte...

Страница 55: ...vents the counter from counting on certain transitions This allows the encoders to count pulses and other specialized applications Encoder inputs can be configured as single ended or pseudo differenti...

Страница 56: ...1 Interrupt has occurred Write 1 to clear STAT_A_NEG Indicates channel A has transitioned from 0x0000 to 0xFFFF Negative rollover 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear...

Страница 57: ...82C54 TC A1 2 82C54 TC A0 1 Reserved 0 25 MHz INCENCn_MODE This register selects the mode of operation for the Incremental Encoder 15 8 PHASE_FLT 7 0 RW 0 7 6 5 4 3 2 1 0 Reserved DIFF FILTE R JOIN I...

Страница 58: ...E registers are not held 1 VALUE registers are held ENA Enable for this incremental encoder 0 Encoder is disabled 1 Encoder is enabled INCENCn_VALUEy Returns the current value of this incremental enco...

Страница 59: ...y cycle outputs For example if a 1 MHz clock is used for the period clock and the PERIOD register is set to its maximum value and a 10 MHz clock is used for the width clock the duty cycle range is 0 t...

Страница 60: ...Mn_PERIOD Sets the maximum width of the PWM outputs If the period clock and width clock are the same PWMn_CLK PER_CLK PWMn_CLK WIDTH_CLK this will also set the PWM period See Figure 13 on page 59 for...

Страница 61: ...rogram Each counter operating mode is set by control word programming The control word format is outlined below Table 12 Select Counter SC 1 0 Selection of set counter SC 1 0 Set Contents 00 Counter 0...

Страница 62: ...level until the input of N 1 the clock pulse after the initial count value writing Count value writing during counting The count value is loaded in the CE at the falling edge of the next clock and co...

Страница 63: ...value is reloaded at the falling edge of the clock pulse succeeding the next gate trigger The gate can be used for counter synchronization in this way Count value load timing After the control word an...

Страница 64: ...ck pulse and then restores H level Count value load timing Even after the control word and initial count value are written loading to the CE does not occur until the input of the clock pulse succeedin...

Страница 65: ...RTD Embedded Technologies Inc www rtd com 65 DMx820 User s Manual...

Страница 66: ...lue is latched by writing counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all The output latch OL of the selected counter latches the coun...

Страница 67: ...e counter selection occurs according to bits D3 D2 and D1 It is possible to latch multiple counters by using the read back command Latching of a read counter is automatically canceled but other counte...

Страница 68: ...ult A Control word register writing Null count 1 B Count register CR writing Null count 1 C New count loading to CE CR CE Null count 0 Note The null count operation for each counter is independent Whe...

Страница 69: ...s time point is ignored and the first latch command is valid If both the count and status are latched the status latched in the first counter read operation is read The order of count latching and sta...

Страница 70: ...x90 DMADPR0 DMA Channel 0 Descriptor Pointer DMA Channel 1 0x94 DMAMODE1 DMA Channel 1 Mode 0x98 0x9C DMAPADR1 DMA Channel 1 PCI Address 0x9C 0xA0 DMALADR1 DMA Channel 1 Local Address 0xA0 0x98 DMASIZ...

Страница 71: ...ransfers data when its DREQ0 input is asserted Asserts DACK0 to indicate the current Local Bus transfer is in response to DREQ0 input The DMA Controller transfers Lwords 32 bits of data This may resul...

Страница 72: ...e DMA Controller then moves to the next descriptor in the chain Note Descriptor Memory fields are re ordered when this bit is set Yes Yes 0 x 21 Ring Management Valid Stop Control Value of 0 indicates...

Страница 73: ...chain descriptor Same as DMA Block mode Yes Yes 0h x 2 Interrupt after Terminal Count Writing 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached Writing 0 dis...

Страница 74: ...00b indicates a rotational priority scheme Writing 01b indicates Channel 0 has priority Writing 10b indicates Channel 1 has priority Value of 11b is reserved Yes Yes 00b 00b 31 21 Reserved Yes Do not...

Страница 75: ...sting the Local Bus for reads Nybble values 0h through Eh may be used Refer to Table 17 15 C1PLAF C1LPAE Yes Yes 0h x 27 24 DMA Channel 1 Local to PCI Almost Full C1LPAF Number of full Lword x 2 entri...

Страница 76: ...rupt the Local Bus Master must read the Mailbox Used in conjunction with the Local Interrupt Output Enable bit INTCSR 16 Yes Yes 0 0 4 Power Management Interrupt Enable Writing 1 enables a Local inter...

Страница 77: ...errupt input LINTi is active Yes No 0 0 16 Local Interrupt Output Enable Writing 1 enables Local interrupt output LINTo Yes Yes 1 1 17 Local Doorbell Interrupt Enable Writing 1 enables PCI to Local Do...

Страница 78: ...a Target Abort after 256 consecutive Master Retries to a Target Yes No 1 1 28 Reading 1 indicates that the PCI Bus wrote data to MBOX0 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3...

Страница 79: ...number of modules in the system possible Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorre...

Страница 80: ...ound on the webpage for the PCI Special Interest Group www pcisig com PLX PCI9056 For more information about the PLX PCI9056 PCI Accelerator contact PLX Technologies at www plxtech com 82C54 Timer Cou...

Страница 81: ...ther contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other...

Страница 82: ...ologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Copyright 2018 by RTD Embedded Technologies Inc Al...

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