rtd CMV6486DX100HR, Руководство пользователя

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MASTER* I During a DMA cycle, this active-low signal, indicates that a resource
on the bus is about to drive the data and address lines.
MEMCS16* I Memory Chip Select 16-bit: this line, active low, is controlled by de-
vices mapped in the memory address space and indicates they have a
16-bit bus width.
MEMR* I/O This active-low signal indicates a memory read operation. Devices us-
ing this signal must decode the address on lines LA23..LA17 and
SA19..SA0.
MEMW* I/O This active-low signal indicates a memory write operation. Devices
using this signal must decode the address on lines LA23..LA17 and
SA19..SA0.
OSC O OSCillator: clock with a 70 ns period and a 50% duty cycle. It is a
14.31818MHz always presents.
REFRESH* O This line is active low and indicates that the current bus cycle is a
DRAM refresh cycle. The refresh cycles are activated every 15 micro-
seconds.
RESETDRV O This line, active high, is used to reset the devices on the bus, at power-
on or after a reset command.
SA0..19 O Address bits 0 to 19: these lines are used to address the memory space
and the I/O space. SA0 is the least significant bit while SA19 is the
most significant bit.
SBHE* O This active-low signal indicates a transfer of the most significant data
byte (SD15..SD8).
SD8..15 I/O Data bits: these are the high-byte data bus lines. SD8 is the least sig-
nificant bit; SD15 the most significant bit.
SD0..7 I/O Data bits: these are the low-byte data bus lines. SD0 is the least sig-
nificant bit; SD7 the most significant bit.
SMEMR* O Memory Read command, active low.
SMEMW* O Memory Write command, active low.
SYSCLK O System Clock, 8.0MHz with a 50% duty cycle. Only driven during ex-
ternal bus cycles.
TC O Terminal Count: this line is active high and indicates the conclusion
of a DMA transfer.