42
The following table lists signals of the AT portion of the PC/104 bus.
Notes:
Keying pin positions are blanked to prevent misalignment of stacked modules. This is a feature of
the PC/104 specification and should be implemented on all mating PC/104 modules.
Signals marked with (*) are active-low.
0V is ground
All bus lines can drive a maximum current of 6mA at TTL voltage levels.
PC/104 AT Bus Connector, CN2
Pin
Row C
Row D
1
0V
0V
2
SBHE*
MEMCS16*
3
LA23
IOCS16*
4
LA22
IRQ10
5
LA21
IRQ11
6
LA20
IRQ12 Used in-
ternally
7
LA19
IRQ15
8
LA18
IRQ14
9
LA17
DACK0*
10
MEMR*
DRQ0
11
MEMW*
DACK5*
12
SD8
DRQ5
13
SD9
DACK6*
14
SD10
DRQ6
15
SD11
DACK7*
16
SD12
DRQ7
17
SD13
+5V*
18
SD14
MASTER*
19
SD15
0V
20
(Keying pin)
0V
Содержание CMV6486DX100HR
Страница 2: ......
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Страница 28: ...28 I O Connections...
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Страница 48: ...48 Configuring Hardware...
Страница 74: ...74 An example BASIC program illustrating EEPROM access is in the file CMV_EE BAS on the cpu Module utility disk...
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Страница 118: ...118 RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Our website www rtd com...