43
PC/104 Bus Signals
The following table contains brief descriptions of the PC/104 bus signals.
Signal
I/O
Description
AEN
O
Address ENable: when this line is active (high), it means a DMA
transfer is being performed and therefore the DMA controller has con-
trol over the data bus, the address bus, and the control lines.
BALE
O
Bus Address Latch Enable, active high. When active, it indicates that
address lines SA0 to SA19 are valid.
DACKx*
O
DMA ACKnowledge x=0-7, active low, used to acknowledge DMA
requests.
DRQx
I
DMA Request x=0-7: these are asynchronous lines used by peripheral
devices to request DMA service. They have increasing priority from
DRQ0 up to DRQ7. A DMA request is performed by setting the DRQ
line high and keeping it high until the corresponding DACK line is ac-
tivated.
ENDXFR*
I/O
This is the only synchronous signal of the PC/104 bus and it is active
low. It indicates that the current bus cycle must be performed with 0
wait states. It is used only for 16-bit boards.
IOCHCHK*
I
I/O Channel Check, active low, indicates an error condition that can-
not be corrected.
IOCHRDY
I
I/O Channel Ready: this line, usually high (ready) is pulled to a low
level by devices which need longer bus cycles.
IOCS16*
I
I/O Chip Select 16-bit: this line, active low, is controlled by devices
mapped in the I/O address space. It indicates they have a 16-bit bus
width.
IOR*
O
I/O Read, active low, indicates when the devices present on the bus
can send their information on the data bus.
IOW*
O
I/O Write, active low. When active, it allows the peripheral devices to
read data present on the data bus.
IRQx
I
Interrupt Request: x = 2 to 15, active on rising edge. IRQ15 has top
priority; the other lines have decreasing priority starting from IRQ14
down to IRQ2. An interrupt request is performed by changing the lev-
el of the corresponding line from low to high and keeping it high until
the microprocessor has recognized it.
KEY
N/A
These locations contain mechanical keying pins to help prevent incor-
rect connector insertion.
LA23..LA17
O
These signals select a 128kbyte window in the 16Mbyte address space
available on the bus.
Содержание CMV6486DX100HR
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Страница 48: ...48 Configuring Hardware...
Страница 74: ...74 An example BASIC program illustrating EEPROM access is in the file CMV_EE BAS on the cpu Module utility disk...
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Страница 118: ...118 RTD Embedded Technologies Inc 103 Innovation Blvd State College PA 16803 0906 USA Our website www rtd com...
