R01UH0823EJ0100 Rev.1.00
Page 757 of 1823
Jul 31, 2019
RX23W Group
27. Compare Match Timer (CMT)
27.2.4
Compare Match Counter (CMCNT)
The CMCNT counter is a readable/writable up-counter.
When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3)
bit is set to 1, the CMCNT counter starts counting up using the selected clock.
When the value in the CMCNT counter and the value in the CMCOR register match, the CMCNT counter is set to
0000h. At the same time, a compare match interrupt (CMIn) (n = 0 to 3) is generated.
27.2.5
Compare Match Constant Register (CMCOR)
The CMCOR register is a readable/writable register to set a value for compare match with the CMCNT counter.
Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address(es): CMT0.CMCOR 0008 8006h, CMT1.CMCOR 0008 800Ch, CMT2.CMCOR 0008 8016h, CMT3.CMCOR 0008 801Ch
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1