Renesas M16C FAMILY, Руководство пользователя

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Rev.2.00 Oct 16, 2006 page 49 of 354
REJ09B0340-0200
M30245 Group 2. Clock-Synchronous Serial I/O
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.3.2.
Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figures
2.3.9 and 2.3.10 show the set-up procedures.
2.3.3 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
Item Item Set-up Set-up
Transfer clock
source
CLK polarity
Internal clock (f
1
/ f
8
/ f
32
)
External clock (CLKi pin)
RTS function RTS function enabled
RTS function disabled
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
O
O
O
Continuous receive
mode
Disabled
Enabled
O
Transfer clock LSB first
MSB first
O
Data logic select
function
No reverse
Reverse
O
T
X
D, R
X
D I/O
polarity reverse bit
No reverse
Reverse
O
Table 2.3.2. Choosed functions
(1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
________
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
Operation
Note
_______
checking that the RTS output has gone to “L” level).
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
• Set CLKi and RxDi pins' port direction register to “0”.