Renesas M16C FAMILY, Руководство пользователя

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Rev.2.00 Oct 16, 2006 page 98 of 354
REJ09B0340-0200
M30245 Group 2. Serial Interface Special Function
2.5.3 Operation of Serial Interface Special Function (reception in master mode with
clock delay)
Operation
Note
Item Item Set-up Set-up
Transfer clock
source
Internal clock (f
1
/ f
8
/ f
32
)
External clock (CLKi pin)
O
SSi port function
enable
SSi function disabled
SSi function enabled
O
O
Clock phase set Without clock delay
With clock delay
O
Continuous receive
mode
Disabled
Enabled
O
CLK polarity
Output reception data at
the falling edge of the
transfer clock
Output reception data at
the rising edge of the
transfer clock
O
Serial input port set
T
X
Di, R
X
Di selected
(master mode)
ST
X
Di, SR
X
Di selected
(slave mode)
Item
Table 2.5.2. Choosed functions
In receiving data in serial interface special function master mode, choose functions from those listed in
Table 2.5.2. Operations of the circled items are described below. Figure 2.5.11 shows the operation
timing, and Figures 2.5.12 and 2.5.13 show the set-up procedures.
____
(1) Set an SS port of the transmitter side IC to output “L” level.
(2) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
and the transmit enable bit to “1”, makes the data receivable status ready.
(3) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
(4) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
register is transmitted to the UARTi receive buffer register. At this time, the receive complete
flag and the UARTi receive interrupt request bit goes to “1”.
(5) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
is read.
• Set RxDi pins' port direction register to “0”.
_____
• Set SSi pin to “H” level. If “L” level is input to the pin, a fault error will be generated.