Renesas M16C FAMILY, Руководство пользователя

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Rev.2.00 Oct 16, 2006 page 121 of 354
REJ09B0340-0200
M30245 Group 2. Frequency synthesizer (PLL)
2.7 Frequency synthesizer (PLL)
This paragraph explains the registers setting method and the notes related to the frequency synthesizer
(PLL circuit).
2.7.1 Overview
The frequency synthesizer generates the 48MHz clock that is necessary for the USB block and the f
SYN
clock. These clocks are a multiple of the external input standard clock f(X
IN
). Figure 2.7.1 shows the
frequency synthesizer circuit block diagram.
Figure 2.7.1. Frequency synthesizer circuit block diagram
FSP FSM FSC
f(X
IN
)
f
PIN
f
VCO
f
SYN
f
USB
FSD FSCCR
FSCCR0
USBC5
EN
Data Bus
Frequency
Multiplier
(03DF
16
) (03DC
16
) (03DD
16
)
(03DE
16
)
(03DB
16
)
8 Bit
8 Bit
8 Bit
Frequency
Divider
Prescaler
LS
(1) Related Registers
Figure 2.7.2 shows a memory location diagram for the frequency synthesizer related registers; Fig-
ures 2.7.3 and 2.7.4 show the composition of the frequency synthesizer related registers.
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
000A
16
Frequency synthesizer clock control register (FSCCR)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register (FSM)
Frequency synthesizer prescaler register (FSP)
Frequency synthesizer divide register (FSD)
Protect register (PRCR)
Figure 2.7.2. Memory map of frequency synthesizer related registers