Renesas M16C FAMILY, Руководство пользователя

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Rev.2.00 Oct 16, 2006 page 142 of 354
REJ09B0340-0200
M30245 Group 2. USB function
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USB endpoint x(x=0 to 4) OUT FIFO data register
Endpoints 0 to 4 respectively have their OUT FIFOs. When data are received from the host PC, read
the receive data from these registers. Access these registers in word cycle or byte cycle to the lower
byte.
The configuration of USB x(x=0~4) OUT FIFO data register is shown in Figure 2.8.13.
Figure 2.8.13. USB x(x=0~4) OUT FIFO data register
Figure 2.8.14. Endpoint x IN/OUT FIFO mapping
Bit Symbol Bit Name Function
R W
Symbol
EPxO (x = 0 - 4) Address
02E2
16
, 02E6
16
, 02EA
16
,
02EE
16
, 02F2
16
When reset
N/A
USB Endpoint x OUT FIFO Data register
b7
(b15)
(b8)
b0
DATA_15-0
b7 b0
EP0 OUT FIFO Data
O X
Note 1: Writing to this register might cause a system error.
Note 2: Read only from this register with a Word command or a Byte command to the lower 8
bits. Do not read a byte of data from the upper 8 bits. (b8 - b15)
Read receive data
from this register
The endpoint x IN/OUT FIFO mapping is shown in Figure 2.8.14.
This area is allocated for IN/OUT FIFOs of the endpoint 1 to 4.
The FIFO size and start position can be specified for every 64-byte by
USB EPx IN FIFO configuration register and USB EPx OUT FIFO configuration register.
3328 bytes
64 bytes
64 bytes
256 bytes
Endpoint 0
IN FIFO: 128 bytes,
OUT FIFO: 128 bytes
Endpoint FIFO