Radstone PME 68-1B, Руководство пользователя

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Table 5 Parallel I/O Interface Registers
Affected
Address Mode By Reset Using
0E0001 R/W Y Port General Control Register (PGCR)
0E0003 R/W Y Port Service Request Register (PSRR)
0E0005 R/W Y Port A Data Direction Register (PADDR)
0E0007 R/W Y Port B Data Direction Register (PBDDR)
0E0009 R/W Y Port C Data Direction Register (PCDDR)
0E000B R/W Y Port Interrupt Vector Register (PIVR)
0E000D R/W Y Port A Control Register (PACR)
0E000F R/W Y Port B Control Register (PBCR)
0E0011 R/W** N Port A Data Register (PADR)
0E0013 R/W** N Port B Data Register (PBDR)
0E0015 R N Port A Alternate Register (PAAR)
0E0017 R N Port B Alternate Register (PBAR)
0E0019 R/W N Port C Data Register (PCDR)
0E001B R/W* Y Port Status Register (PSR)
0E0021 R/W Y Timer Control Register (TCR)
0E0023 R/W Y Timer Interrupt Vector Register (TIVR)
0E0027 R/W Y Counter Preload Register High (CPRH)
0E0029 R/W N Counter Preload Register Middle(CPRM)
0E002B R/W N Counter Preload Register Low (CPRL)
0E002F R N Count Register High (CNTRH)
0E0031 R N Count Register Middle (CNTRM)
0E0033 R N Count Register Low (CNTRL)
0E0035 R/W* Y Timer Status Register (TSR)
* A Write to this register may perform a special status reset operation.
** Affected by Read Cycle. (mode dependent e.g. port interface or timer.)
PIT Interrupts
The PIT is able to interrupt the CPU. This allows it to operate in fully asynchronous
mode as well as being able to use the timer as a time base for multi-tasking software.
The general purpose 24-bit timer, with its 5-bit prescaler, can be used as an output for
programmable frequencies, with internal or external clocks, as a watchdog and as a
normal time base.
The PIT can interrupt under parallel operation, or if port C is used in timer mode, under
timer operation. A special pin is used for each and is selectable using BR18 links 1, 2
and 3. Both interrupts are enabled under default conditions.
PME68-1B Manual
Page 29 Issue 5