RadiSys EPC-5A, Справочное руководство по аппаратному и программному обеспечению

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Chapter 6: The VMEbus Interface
Page 75
VME Interrupt Enable Register (8153h)
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR
This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes
that the corresponding interrupt is enabled. If any bit in this register is a 1 and the
corresponding bit in the interrupt state register is a 0, the EPC-5A IRQ10 interrupt is
asserted. Software may then examine the interrupt and event state registers to
determine the cause.
VME Event State Register (8154h)
1 1 1 1 1 ACFA BERR SYSF
Similar to the interrupt state register, this register defines additional conditions that
may result in an IRQ10 interrupt. If the bit is 0, the condition is present.
ACFA VMEbus ACFAIL is asserted.
BERR An access from the EPC-5A to the VMEbus was terminated with a BERR
(bus error).
SYSF VMEbus SYSFAIL is asserted.
All bits are read-only except BERR. BERR is a sticky bit that is cleared whenever an
access from the EPC-5A is terminated by a bus error, and remains clear (0) unless
changed by software (by writing any value to this register).
VME Event Enable Register (8155h)
1 1 1 1 1 ACFA BERR SYSF
This is a mask of the interrupt conditions in the event state register. A 1 denotes that
the corresponding event is enabled as an interrupt. If any bit in this register is a 1 and
the corresponding bit in the event state register is a 0, the EPC-5A IRQ10 interrupt is
asserted. Software may then examine the interrupt and event state registers to
determine the cause.