RadiSys EPC-5A, Справочное руководство по аппаратному и программному обеспечению

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Chapter 6: The VMEbus Interface
Page 73
WRDY Write ready. If set, the message registers are armed for an incoming mes-
sage. When a write occurs into the message-low register, WRDY is cleared
and the MSGR interrupt condition is asserted.
When the response register is read from the VMEbus, the current value of the register
is read, and then LOCK is cleared. The protocol for sending a message to the
EPC-5A, if there are multiple potential senders, is the following. The sender first
reads the response register. If both WRDY and LOCK are 1, the sender may then
proceed to send the message. For a 16-bit message, the sender writes into the
message-low register. For a 32-bit message, the sender writes first into the message-
high register and then the message-low register.
Message High Register (814Ch & 814Dh)
RAM Lower
RAM Upper
This register is an extension of the following register for 32-bit messages. An access
to this register clears flag ABMH in the response register.
Message Low Register (814Eh & 814Fh)
RAM Lower
RAM Upper
This register is typically used as an incoming message register by doing a D16 write
into it from the VMEbus (this register, as are many others, is mapped into the
VMEbus A16 address space, as discussed later).
VME A31-24 Address Register (8150h)
VMEbus Address bits 31-24 (WA31-24)
This register is one of several that supply the VMEbus address bits when the EPC-5A
makes an access in its memory window. This register supplies VME address bits A31-
A24.