RadiSys EPC-5A, Справочное руководство по аппаратному и программному обеспечению

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EPC-5A Hardware & Software Reference Manual
Page 68
6 6
VME Event Enable Register
DONE AS DS0 DS1 1 1 (res.) 1
8156h
Module Status/Control Register
1 1 1 1 1 INTERRUPT-OUT
815Fh
Interrupt Generator Register
Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing
to it has no effect. Unless otherwise noted below, all registers and bit values are
readable and writeable.
VMEbus and Memory Controller Configuration (8104h)
MEMSIZE VME
This register controls the DRAM memory controller and certain aspects of BIOS write
protection and the VMEbus interface. The bits in this register are cleared by an “AT
reset” (that is, when the RESET button is pushed or power is applied to the system).
MEMSIZE Memory Size. These bits tell the memory controller how much SIMM
DRAM memory is present on the EPC-5A. This field is set by the
BIOS when power is applied to the EPC-5A, and contains one of the
following values: 001 = 4 MB, 010 = 8 MB, 111 = 16 MB, 110 = 32
MB. Larger memory sizes are not yet defined.
VME If set (1), this bit allows VME accesses through the DOS window or
through shared memory above 256 MB in protected mode. When
clear (0), the VMEbus cannot be accessed. This bit is automatically
set by the BusManager software when using EPConnect.
✏
Note
Except for the VME access bit, the bits in this register are
manipulated by the BIOS. User software should manipulate only
the VME access bit in this register.