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User’s Manual
81
When operating in 32 kHz mode it is also possible to further divide the clock to a fre-
quency as low as 2 kHz, further reducing execution speed and current consumption.
It is anticipated that these measures would reduce operating current consumption to as low as
20 µA plus some additional leakage that would be significant at high operating temperatures.
Global Power Save Control Register
(GPSCR)
(Address = 0x0D)
Bit(s)
Value
Description
7:5
000
Self-timed chip selects are disabled.
001
This bit combination is reserved and should not be used.
01x
This bit combination is reserved and should not be used.
100
296nS self-timed chip selects (192nS best case, 457nS worst case).
101
234nS self-timed chip selects (151nS best case, 360nS worst case).
110
171nS self-timed chip selects (111nS best case, 264nS worst case).
111
109nS self-timed chip selects (71nS best case, 168nS worst case).
4
0
Normal Chip Select operation.
1
Short Chip Select timing when dividing main oscillator by 4, 6, or 8.
3
x
This bit is reserved and should not be used.
2:0
000
The 32KHz clock divider is disabled.
001
This bit combination is reserved and should not be used.
01x
This bit combination is reserved and should not be used.
100
32KHz oscillator divided by two (16.384KHz).
101
32KHz oscillator divided by four (8.192KHz).
110
32KHz oscillator divided by eight (4.096KHz).
111
32KHz oscillator divided by sixteen (2.048KHz).
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