108
Rabbit 3000 Microprocessor
1
0
Normal operation.
1
For Root access, invert A19 before MBxCR (bank select) decision.
0
0
Normal operation.
1
For Root access: invert A16
Table 8-5. MMU Expanded Code Register (MECR = 18h)
MMU Expanded Code Register
(MECR)
(Address = 0x18)
Bit(s)
Value
Description
7:3
These bits are ignored for write, and return zeros when read.
2:0
0xx
Normal operation.
100
For an XPC access, use MB0CR independent of A19-A18.
101
For an XPC access, use MB1CR independent of A19-A18.
110
For an XPC access, use MB2CR independent of A19-A18.
111
For an XPC access, use MB3CR independent of A19-A18.
Table 8-4. MMU Instruction/Data Register (MMIDR =010h) (continued)
MMU Instruction/Data Register
(MMIDR)
(Address = 0x10)
Bit(s)
Value
Description
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