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Rabbit 3000 Microprocessor
7.4 Chip Select Options for Low Power
Some types of flash memory and RAM consume power whenever the chip select is
enabled even if no signals are changing. The Rabbit 3000 has optionally enabled modifi-
cations to the chip select behavior that reduce this unnecessary power consumption when
the Rabbit 3000 is running at reduced clock speed.
When the processor clock is divided (by 4, 6, or 8) so as to run at a lower speed the short
chip select option can be enabled. When short chip select is enabled the chip select delays
turning on until the end of the of the memory cycle when it turns on for the last 2 undi-
vided clocks. If the clock is divided by 6 the memory read cycle with no wait states would
normally be 12 undivided clocks long. With the short chip select the chip select is on for
only 2/12 clocks for a memory duty cycle of 1/6. If wait states are added the duty cycle is
reduced even more. For example if there is one wait state and the clock is divided by 6
then the memory bus cycle will be 18 undivided clocks long and the duty cycle will be
2/18=1/9 with the short chip select option enabled.
When the 32.768 kHz clock is used as the main processor clock (sleepy mode) the mem-
ory duty cycle can be reduced by enabling a self-timed chip select mode. When the
32.768 kHz clock is used the clock period is approximately 32 microseconds and a nor-
mal memory read cycle without wait states will be approximately 64 microseconds. No
more than a few hundred nanoseconds are needed to read the memory. The main oscillator
is normally shut down when operating at 32 kHz and no faster clock is available to time
out a short chip select cycle. To provide for a low memory duty cycle a chip select and
memory read can take place under control of a delay timer that is on the chip. The cycle
starts at the start of the final 64 microsecond clock of the memory cycle and can be set to
enable chip select for a period in the range of 70 to 200 nanoseconds. The data is clocked
in early at the end of the delay driven cycle. The chip select duty cycle is very small, about
0.2/128=1/600.
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