Rabbit 3000, Руководство пользователя

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User’s Manual 127
The following registers are described in Table 9-14 and in Table 9-15.
•
PFDR—Port F data register. Reads value at pins. Writes to port F preload register.
•
PFDDR—Port F data direction register. Set to "1" to make corresponding pin an output.
This register is zeroed on reset.
•
PFFR—Port F function register. Set bit to "1" to enable alternate output function. Bits
7-4 enable the PWM outputs and bits 1-0 enable synchronous serial ports C and D
clock outputs for when the serial port is configured for internal clock generation.
•
PFCR—Parallel Port F control register. This register is used to control the clocking of
the upper and lower nibble of the final output register of the port. On reset, bits 0, 1, 4,
and 5 are reset to zero.
On reset, the data direction register is zeroed, making all pins inputs. In addition certain
bits in the control register are zeroed (bits 0,1,4,5) to ensure that data is clocked into the
output registers when loaded. All other registers associated with port F are not initialized
on reset.
Table 9-15. Parallel Port F Control Register (adr = 03Ch)
Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0
x,x
00—clock upper nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2
x,x
00—clock lower nibble on pclk/2
01—clock on timer A1
10—clock on timer B1
11—clock on timer B2