Quectel Smart Module Series, Проектирование аппаратного обеспечения

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Smart Module Series
SA800U-WF Hardware Design
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3.11. PCIe Interfaces
SA800U-WF provides two PCIe interfaces. PCIe0 is a Gen 2 1-lane interface that transmits up to
5 Gbps/lane. PCIe1 is a Gen 3 1-lane interface that transmits up to 8 Gbps/lane.
Table 13: Pin Definition of PCIe Interfaces
Pin Name Pin No. I/O Description Comment
PCIE0_RST_N J1-1 DO PCIe0 reset
PCIE0_WAKE_N J1-3 DI PCIe0 wakes up host
PCIE0_CLKREQ_N J1-5 DI PCIe0 clock request
PCIE0_REFCLK_P J1-15 AO PCIe0 reference clock (+)
Control the characteristic
impedance as 85
Ω.
PCIE0_REFCLK_M J1-17 AO PCIe0 reference clock (-)
PCIE0_TX_P J1-11 AO PCIe0 transmit (+)
PCIE0_TX_M J1-9 AO PCIe0 transmit (-)
PCIE0_RX_P J1-21 AI PCIe0 receive (+)
PCIE0_RX_M J1-23 AI PCIe0 receive (-)
PCIE1_RST_N J1-107 DO PCIe1 reset
PCIE1_WAKE_N J1-111 DI PCIe1 wakes up host
PCIE1_CLKREQ_N J1-109 DI PCIe1 clock request
PCIE1_REFCLK_P J1-121 AO PCIe1 reference clock (+)
Control the characteristic
impedance as 85
Ω.
PCIE1_REFCLK_M J1-123 AO PCIe1 reference clock (-)
PCIE1_TX_P J1-129 AO PCIe1 transmit (+)
PCIE1_TX_M J1-127 AO PCIe1 transmit (-)
PCIE1_RX_P J1-115 AI PCIe1 receive (+)
PCIE1_RX_M J1-117 AI PCIe1 receive (-)