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Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 25 / 106
VDISP_P
J4-29
PO
Display bias
output (+)
VDISP_M
J4-30
PO
Display bias
output (-)
LCD_RST
J2-62
DO
LCD reset
V
OL
max = 0.45 V
V
OH
min = 1.35 V
Active low.
1.8 V power
domain.
LCD_TE
J2-60
DI
LCD tearing
effect
V
IL
max = 0.63 V
V
IH
min = 1.17 V
1.8 V power
domain.
DSI0_CLK_N
J2-26
AO
LCD0 MIPI clock
(-)
100
Ω differential
impedance.
DSI0_CLK_P
J2-28
AO
LCD0 MIPI clock
(+)
DSI0_LN0_N
J2-38
AO
LCD0 MIPI lane
0 data (-)
DSI0_LN0_P
J2-40
AO
LCD0 MIPI lane
0 data (+)
DSI0_LN1_N
J2-32
AO
LCD0 MIPI lane
1 data (-)
DSI0_LN1_P
J2-34
AO
LCD0 MIPI lane
1 data (+)
DSI0_LN2_N
J2-20
AO
LCD0 MIPI lane
2 data (-)
DSI0_LN2_P
J2-22
AO
LCD0 MIPI lane
2 data (+)
DSI0_LN3_N
J2-14
AO
LCD0 MIPI lane
3 data (-)
DSI0_LN3_P
J2-16
AO
LCD0 MIPI lane
3 data (+)
DSI1_CLK_N
J2-21
AO
LCD1 MIPI clock
(-)
DSI1_CLK_P
J2-19
AO
LCD1 MIPI clock
(+)
DSI1_LN0_N
J2-13
AO
LCD1 MIPI lane
0 data (-)
DSI1_LN0_P
J2-15
AO
LCD1 MIPI lane
0 data (+)
DSI1_LN1_N
J2-37
AO
LCD1 MIPI lane
1 data (-)
DSI1_LN1_P
J2-39
AO
LCD1 MIPI lane
1 data (+)