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Smart Module Series
SA800U-WF Hardware Design
SA800U-WF_Hardware_Design 54 / 106
3.10. UART Interface
The module provides one debug UART used for debugging by default. The following table shows the pin
definition of debug UART interface.
Table 12: Pin Definition of Debug UART Interface
Debug UART is a 2-wire UART interface of 1.8 V power domain. A level translator chip should be used if
your application is equipped with a 3.3 V UART interface. The level translator chip TXS0102DCUR
provided by Texas Instruments is recommended. The following figure shows a reference design.
VCCA
VCCB
OE
A1
A2
GND
B1
B2
VREG_S4A_1V8
DBG_RXD
DBG_TXD
RXD_3.3 V
TXD_3.3V
VDD_3.3V
TXS0102DCUR
C1
100 pF
C2
U1
100 pF
Figure 17: Reference Circuit with Level Translator Chip
The following figure is an example of connection between SA800U-WF and PC. A level translator and an
RS-232 level translator chip is recommended to be added between the module and PC, as shown below.
TXS0102DCUR
RXD_3.3V
VCCA
Module
GND
GND
1.8 V
VCCB
3.3 V
DIN1
ROUT3
ROUT 2
ROUT1
DIN4
DIN3
DIN2
DIN 5
FORCEON
3.3 V
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
RIN3
RIN2
RIN1
VCC
GND
OE
SN65C3238
DB-9
TXD
RXD
GND
DBG_TXD
DBG_RXD
TXD_1.8V
RXD_1.8V
/FORCEOFF
/INVALID
R1OUTB
TXD_3.3V
Figure 18: RS-232 Level Match Circuit
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
J2-137
DO
Debug UART transmit
1.8 V power domain.
DBG_RXD
J2-135
DI
Debug UART receive