BIOS Setup Information
ROBO-8714VG2A User’s Manual
4-13
4.6
Advanced Chipset Feature
This section allows you to configure the system based on the specific features of the
Intel 875P and 6300ESB Chipset. This chipset manages bus speeds and access to
system memory resources, such as DRAM (DDR SDRAM) and the external cache. It
also coordinates communications between the conventional the PCI-X bus. It must
be stated that these items should never need to be altered. The default settings
have been chosen because they provide the best operating conditions for your
system. The only time you might consider making any changes would be if you
discovered that data was being lost while using your system.
Phoenix- AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable
[By SPD]
X CAS Latency Time
2.5
X Active to Precharge Delay
7
X DRAM RAS# to CAS# Delay
3
X DRAM RAS# Precharge
3
Memory Frequency For
[Auto]
System BIOS Cacheable
[Enabled]
Video BIOS Cacheable
[Enabled]
Memory Hole At 15M-16M
[Disabled]
Delayed Transaction
[Enabled]
Delay Prior to Thermal
[16 Min]
AGP Aperture Size (MB)
[64]
Init Display First
[PCI Slot]
TV-Out Mode
[NTSC]
DRAM Data Integrity Mode
ECC
Menu Level
f
↑↓→←
: Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
This chipset settings deal with CPU access to dynamic random access memory
(DRAM). The default timings have been carefully chosen and should only be altered
if data is being lost. Such a scenario might well occur if your system had mixed
speed DRAM chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
DRAM Timing Selectable
This option provides DIMM plug-and-play support by serial presence detect (SPD)
mechanism via the system management bus (SMBUS) interface.
The choice: Manual, By SPD.
