PLX Technology PEX 8647-AA RDK, Справочник по аппаратуре

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PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved
iii
C
ONTENTS
1. General Information ............................................................................................................. 1
1.1 PEX 8647 Features ..................................................................................................... 2
1.2 PEX 8647-AA RDK Features....................................................................................... 3
2. PEX 8647-AA RDK Hardware Architecture ......................................................................... 4
2.1 PCI Express Gen 2 Connections ................................................................................. 5
2.1.1 PEX 8647 PCI Express Gen 2 Switch .................................................................. 5
2.1.2 PCI Express Card Edge P1 .................................................................................. 7
2.1.3 PCI Express Slot Connectors ............................................................................... 7
2.1.3.1 PCI Express Connector SLOT 1 ....................................................................... 7
2.1.3.2 PCI Express Connector SLOT 2 ....................................................................... 7
2.2 Reference Clock Circuitry ............................................................................................ 7
2.3 Reset Circuitry ............................................................................................................. 8
2.4 Serial EEPROM ........................................................................................................... 8
2.5 I
2
C Interface ................................................................................................................ 8
2.6 Power Distribution ....................................................................................................... 8
2.7 LED Indicators ............................................................................................................. 9
2.7.1 Port Link Status Indication (D10 – D12) ............................................................. 10
2.7.2 Fatal Error Indication (D13) ................................................................................ 10
2.7.3 PEX_INTA# Interrupt Indication (D14) ............................................................... 10
2.7.4 PEX 8647 Voltage Level Monitoring (D8 – D9) .................................................. 10
2.8 GPIO Pins ................................................................................................................. 10
2.9 Upstream Port Select Pins ........................................................................................ 10
2.10 Reserved Pins ........................................................................................................... 11
3. On-Board Connectors, Switches, and Jumpers ................................................................. 12
3.1 DIP Switches ............................................................................................................. 12
3.1.1 I
2
C Address Selection (SW2) ............................................................................. 12
3.2 Push-Button Switches ............................................................................................... 12
3.2.1 Manual Reset# (S1) ........................................................................................... 12
3.3 MidBus Footprints (JP1 – JP6) .................................................................................. 13
3.4 2.5V Header (JP7) ..................................................................................................... 14
3.5 JTAG Header (JP8) ................................................................................................... 14
3.6 I
2
C Port (JP9 – JP10) ................................................................................................ 14
3.7 Reference Clock Header (J1) .................................................................................... 15
3.8 ATX HD Power Connector (J2 – J3) .......................................................................... 15
4. Bill of Materials/ Schematics .............................................................................................. 16