3.7
Reference Clock Header (J1)
Table 3-6. Pin assignment of J1
Pin #
Signal name
1 Refclkp
(+)
2 GND
3 Refclkn
(-)
3.8
ATX HD Power Connector (J2 – J3)
Table 3-7. Pin assignment of J1
Pin #
Signal name
1 +12VDC
2 COM
(GND)
3 COM
(GND)
4 +5VCC
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved
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