PLX Technology PEX 8647-AA RDK, Справочник по аппаратуре

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PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
2 Copyright © 2008 by PLX Technology, Inc. All rights reserved
1.1 PEX 8647 Features
•
48-lane, 3-port PCI Express Gen 2 switch with integrated on-chip 5.0 GT/s SerDes
•
480 GT/s aggregate bandwidth
•
27mm
2
676-ball Flip-Chip Plastic Ball Grid Array (FCBGA) package
•
Typical Power – 3.75W
•
Cut-Thru packet latency of less than 140ns (x16 to x16)
•
Low power SerDes (under 90mW per lane)
•
Fully non-blocking switch architecture
•
Ports configurable as x16, with auto link-width negotiation to x8, x4, x2 and x1
•
Flexible device configuration
o
Configurable via serial EEPROM, I
2
C, hardware strapping, or by the host
•
Maximum packet payload size of 2,048 bytes
•
Lane reversal and polarity reversal support
•
Designate any Port as the
Upstream Port
(Port 0 is recommended)
•
Dynamic Buffer Pool Architecture
•
Dual-Casting (enhances performance by sending date from one ingress port to two egress ports)
•
Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation
•
Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic
density)
•
Lane and polarity reversal
•
Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3
(
with
Vaux not supported)
•
Conventional PCI-compatible Device Power Management states – D0 and D3hot
•
Active State Power Management
•
Quality of Service (QoS)
o
One Virtual Channels (VC0) and Eight Traffic classes (TC)
o
Round-Robin and Weighted Round-Robin Port arbitration
•
Reliability, Availability, Serviceability (RAS) features
o
Electromechanical Interlock supported with Power Enable output
o
Baseline and Advanced Error Reporting capability
o
Performance Monitoring
ƒ Per-Port Payload and Header Counters
ƒ Per-traffic type (write, Read, Completion) Counters
o
JTAG AC/DC boundary scan
o
3-port link status indicators (PEX_PORT_GOOD[8,4,0]#)
o
17 GPIO pins
•
INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support
•
Compliant to the following specifications:
o
PCI Local Bus Specification, Revision 3.0 (PCI r3.0)
o
PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
o
PCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2)
o
PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1)
o
PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
o
PCI Express Card Electromechanical (CEM) Specification, Revision 2.0
o
PCI ExpressCard CEM r2.0)
o
PCI Express Mini Card Electromechanical (CEM) Specification, Revision 1.1
(PCI ExpressCard Mini CEM r1.1)
o
IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,
1990 (IEEE Standard 1149.1-1990)
o
IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
o
IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
o
IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture
Extensions (IEEE Standard 1149.6-2003)
o
The I
2
C-Bus Specification, Version 2.1 (I
2
C Bus v2.1)