2.1.2
PCI Express Card Edge P1
The PEX 8647-AA RDK can plug directly into a x16 PCI Express slot. Port 0, which consists of lane 0 to lane 15,
is connected to the PCI Express Card Edge connector (P1) through two midbus probe footprints (JP5 and JP6).
The PEX 8647-AA RDK uses Port 0 as the upstream port. The card edge provides the main source of +12V and
+3.3V power, along with the reset signal (PERST#) and the system reference clock (REFCLK_P/REFCLK_N).
2.1.3
PCI Express Slot Connectors
The PEX 8647-AA RDK contains two PCI Express slot connectors which connect to the downstream ports of the
PEX 8647. The two downstream ports (port 4 and port 8) are each x16 wide and each is connected to x16 sized
connector. The slots are physically spaced 40.64mm apart in order to allow the insertion of two double slot-wide
endpoints particularly high power and high performance PCI Express graphic cards with SLI or Cross Fire
capabilities. If the number of lanes implemented by the endpoint is less than the sixteen lanes implemented on
the downstream ports of the PEX 8647, they will auto-negotiate to the highest common link width. For example, if
a x8 card plugs into SLOT1, the negotiated link width will be x8. If an x2 card plugs into SLOT2, the negotiated
link width will be x2.
2.1.3.1
PCI Express Connector SLOT 1
Connector SLOT 1 is a vertical-mount (through-hole), x16 PCI Express connector. Cards plugging into SLOT 1
will be perpendicular to the RDK. Lanes 16 to 31 from PEX 8647 are connected to the PCI Express SLOT 1.
Power to SLOT 1 is provided from the ATX hard disk connector J2 and J3.
2.1.3.2
PCI Express Connector SLOT 2
Connector SLOT 2 is a vertical-mount (through-hole) x16 PCI Express connector. Cards plugging into SLOT 2 will
be perpendicular to the RDK. Lanes 32 to 47 from PEX 8647 are connected to the PCI Express SLOT 2. Power to
connector SLOT 2 is provided from the ATX hard disk connector J2 and J3.
2.2
Reference Clock Circuitry
The PEX 8647-AA RDK reference clock circuitry contains a one-to-four differential clock fan out buffer (U2). The
clock fan out buffer is produced by SpectraLinear with part number of CY28400-2. It supports four 100 MHz PCI
Express reference clocks with the option for constant frequency and spread spectrum outputs. When the RDK is
plugged into a PC x16 PCI Express slot, the differential reference clock is taken from the PCIe card-edge, and
distributed to the PEX_REFCLK_P/PEX_REFCLK_N input, two downstream slot connectors, and the reference
clock header. The 3-pin reference clock header J1 provides the reference clock for probing the PCI Express
differential signals on the midbus probe footprints. (See
for details)
x16
x1
6
Figure 2-3. PEX 8647-AA RDK Reference Clock Circuit
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2008 by PLX Technology, Inc. All rights reserved
7
