Pin #
Signal Name
Pin #
Signal Name
36 C5n-Downstream 35
GND
38 GND 37
C6p-Upstream
40 C6p-Downstream 39
C6n-Upstream
42 C6n-Downstream 41
GND
44 GND 43
C7p-Upstream
46 C7p-Downstream 45
C7n-Upstream
48 C7n-Downstream 47
G2 GND
Table 3-3. Midbus probe footprints vs. Lanes of PEX 8647
Midbus Probe Footprint
Lanes of PEX 8647
JP5
Lane 0 – Lane 7
JP6
Lane 8 – Lane 15
JP1
Lane 16 – Lane 23
JP2
Lane 24 – Lane 31
JP3
Lane 32 – Lane 39
JP4
Lane 40 – Lane 47
3.4
2.5V Header (JP7)
This 2-pin header provides the mechanism for 2.5 volt measurement. It is for internal use only. For regular RDKs,
no header will be assembled and instead a wire will be used to connect pin 1-2 of JP7.
3.5
JTAG Header (JP8)
Header JP8 provides a direct connection to the PEX 8647 JTAG interface. The 10-pin connector is designed to
allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller. The pin
assignment for the JTAG header (JP8) is listed on
.
Table 3-4. Pin assignment of JP8
Pin #
Signal name
1 JTAG_TRST
3 JTAG_TDI
5 JTAG_TDO
7 JTAG_TMS
9 JTAG_TCK
2,4,6,8,10 GND
3.6
I
2
C
Port (JP9 – JP10)
Table 3-5. Pin assignment of JP9 and JP10
Pin #
Signal name
1 I2C_SCL
2 GND
3 I2C_SDA
4 NC
PEX 8647-AA RDK Hardware Reference Manual, Version 1.2
14
Copyright © 2008 by PLX Technology, Inc. All rights reserved
