Introduction to the phyCORE-MPC565
© PHYTEC Meßtechnik GmbH 2009 L-647e_2
5
phyCORE-MPC565 Technical Highlights
•
Single Board Computer in subminiature form factor (84 x 57 mm)
according to phyCORE specifications
•
all applicable controller and other logic signals extend to two
high-density 200-pin Molex connectors
•
Freescale embedded PowerPC MPC565 (40/56 MHz clock)
•
Internal Features of the MPC565:
- 32-bit PowerPC core, 40 / 56 MHz CPU speed
- 64-bit Floating Point Unit
- 36 kByte SRAM; capable of battery buffering
- 1 MByte Flash (two independent 512 kByte blocks)
-
four UARTs
-
two SPI interfaces and one J1850 interface
- three CAN 2.0B interfaces
- three TPU with 16 channels each
-
six 16-bit timer systems (MOIS14)
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twelve 16-bit PWM systems (MIOS14)
- dual 10-bit ADC (5µs) with 40 (65) channels (ext. MUX)
-
multi-purpose I/O signals
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JTAG/BDM/Nexus test/debug port
•
Memory Configuration
1
:
- SRAM:
1 MByte to 16 MByte flow-through
synchronous burst-RAM, 32-bit access,
0 wait states, 2-1-1-1 burst mode
-
Flash-ROM:
2/4 MB synchronous burst mode
Flash-EEPROM, 32-bit access
2 MByte to 8 MByte asynchronous
standard Flash-EEPROM, 32-bit access
- I
2
C Memory:
4 kByte EEPROM (up to 32 kByte, alter-
natively I
2
C FRAM, I
2
C SRAM)
•
Other Board-Level Features:
1
:
Please contact PHYTEC for more information about additional module configurations.
