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Firmware version 1.10 - Document version 1.06 - eng
LTDVE1CH-40F | INSTRUCTIONS MANUAL
Allowed values are in the range from 0 to 3 and are listed below. Avoid operation with non-listed
values.
•
When 0x0 a time base of 1 µs is selected (default value)
•
When 0x1 a time base of 10 µs is selected
•
When 0x2 a time base of 100 µs is selected
•
When 0x3 a time base of 1000 µs is selected
Bit fields [15:2] of these registers are unused. When writing these bits, they must be set to zero.
14.2.12. Registers GEN_WIDTH_COUNT[0-1]
Each bit field [9:0] of these two registers holds the actual count for the generation of the pulse width
in the relevant pulse generator.
•
GEN_WIDTH_COUNT0
: pulse width setting for generator 1
•
GEN_WIDTH_COUNT1
: pulse width setting for generator 2
Allowed values are in the range from 1 (default value) to 1023 (maximum value). Avoid operation
with non-allowed values.
According to the time base selected in register
GEN_WIDTH_BASE
[x] and the count set in
GEN_WIDTH_COUNT
[x], the pulse width may be calculated using the following formula:
Width[x] [µs] = value(GEN_WIDTH_BASE[x]) * value(GEN_WIDTH_COUNT[x])
The pulse width may range from 1 µs to 1,023,000 µs with variable absolute resolution.
Bit fields [15:10] of these registers are unused. When writing these bits, they must be set to zero.
14.2.13. Registers OUTPUT_SEL_HI0 and OUTPUT_SEL_HI8
The output multiplexers are used to route the internal signals to the light output and synchronization
output. Each output multiplexer has an independent selector.
The selector of a specific output multiplexer is a 32 bits binary number, split on a pair of contiguous
Modbus registers named
OUTPUT_SEL_HI
[x] and
OUTPUT_SEL_LO
[x].
The
OUTPUT_SEL_HI
[x] registers contain the upper sixteen bits of the selectors, while the
OUTPUT_SEL_LO
[x] registers contain the remaining lower sixteen bits of the selectors.
•
OUT_SEL_HI0
: upper sixteen bits of output multiplexer 1 selector (light LD)
•
OUT_SEL_HI8
: upper sixteen bis of output multiplexer 9 selector (sync. output SH)
Allowed values for the selectors of the output multiplexers are listed below. Avoid operation with non-
listed values.
•
When 0x0000:0000 the output multiplexer is disabled (default value)
•
When 0x0000:0001 pulse generator 1 output is selected
•
When 0x0000:0002 pulse generator 2 output is selected
•
When 0x0001:0000 filtered input TR is selected
•
When 0x0100:0000 the output is always active (continuous)
Bit fields [15:9] and [7:1] of these registers are unused. When writing these bits, they must be set to
zero.
