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Firmware version 1.10 - Document version 1.06 - eng
LTDVE1CH-40F | INSTRUCTIONS MANUAL
13. Wiring diagrams ................................................................................... 20
13.1. Wiring example #1: controller triggers camera
......................................................
20
13.2. Wiring example #2: camera triggers controller
......................................................
21
14. Operation .............................................................................................. 22
14.1. Operation with Modbus
.........................................................................................
22
14.1.1. Comparison of Modbus/RTU, Modbus/TCP and Modbus/UDP
................................... 22
14.1.2. Supported function codes
............................................................................................... 22
14.1.3. Read Holding Registers (0x03)
...................................................................................... 23
14.1.4. Write Single Register (0x06)
.......................................................................................... 23
14.1.5. Write Multiple Registers (0x10)
.................................................................................... 23
14.2. Register file
...........................................................................................................
23
14.2.1. Register DEVICE_TYPE
............................................................................................... 37
14.2.2. Register BOOT_VERSION
........................................................................................... 37
14.2.3. Register MCU_VERSION
............................................................................................. 37
14.2.4. Register FPGA_VERSION
............................................................................................ 37
14.2.5. Register BOARD_VERSION
........................................................................................ 37
14.2.6. Register OSC_PERIOD
................................................................................................. 37
14.2.7. Register FILTER_SEL0
................................................................................................. 37
14.2.8. Registers INPUT_SEL[0-1]
........................................................................................... 37
14.2.9. Registers GEN_DELAY_BASE[0-1]
............................................................................ 38
14.2.10. Registers GEN_DELAY_COUNT[0-1]
....................................................................... 38
14.2.11. Registers GEN_WIDTH_BASE[0-1]
.......................................................................... 38
14.2.12. Registers GEN_WIDTH_COUNT[0-1]
...................................................................... 39
14.2.13. Registers OUTPUT_SEL_HI0 and OUTPUT_SEL_HI8
............................................ 39
14.2.14. Registers OUTPUT_SEL_LO0 and OUTPUT_SEL_LO8
.......................................... 40
14.2.15. Register PRT_CNT_ON0
............................................................................................ 40
14.2.16. Register PRT_ENA_ON0
............................................................................................ 40
14.2.17. Register PRT_CNT_OFF0
........................................................................................... 40
14.2.18. Register PRT_ENA_OFF0
........................................................................................... 40
14.2.19. Register CUR_RANGE0
............................................................................................. 40
14.2.20. Register CUR_VALUE0
.............................................................................................. 41
14.2.21. Register RS485_MODBUS_ADDR
............................................................................ 41
14.2.22. Register RS485_LINE_SPEED
................................................................................... 41
14.2.23. Register RS485_LINE_PARITY
................................................................................. 41
14.2.24. Registers ETH_MAC_ADDR[0-2]
.............................................................................. 42
14.2.25. Registers ETH_HOSTNAME[0-7]
.............................................................................. 42
14.2.26. Register ETH_DHCP_ENABLE
................................................................................. 42