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One Stop Systems, Inc.                                                                                                          OSS-wanPCI-CxT1E1 User Manual  

Rev. A    

   

                                 6 

Connectors (continued) 

The pin-out for the PCI edge connector is show below 

 

 

A B 

Pin 

 Pin 

TRST#

  

12V

  

1

 

  

2

 

+12V

  

TCK

  

TMS

  

GND

  

3

 

  

4

 

TDI

  

TDO

  

+5V

  

+5V

  

5

 

  

6

 

INTA#

  

+5V

  

INTC#

  

INTB#

  

7

 

  

8

 

+5V

  

INTD#

  

Reserved

  

PRSNT1#

  

9

 

  

10

 

VC(I/O)

  

Reserved

  

Reserved

  

PRSNT2#

  

11

 

  

12

 

Keyway

  

Keyway

  

Keyway

  

Keyway

  

13

 

  

14

 

Reserved

  

Reserved

  

RST#

  

GND

  

15

 

  

16

 

V(I/O)

  

CLK

  

GNT#

  

GND

  

17

 

  

18

 

GND

  

REQ#

  

Reserved

  

V

 

(I/O)

  

19

 

  

20

 

AD[30]

  

AD[31]

  

+3.3V

  

AD[29]

  

21

 

  

22

 

AD[28]

  

GND

  

AD[26]

  

AD[27]

  

23

 

  

24

 

GND

  

AD[25]

  

AD[24]

  

+3.3V

  

25

 

  

26

 

IDSEL

  

C/BE[3]#

  

+3.3V

  

AD[23]

  

27

 

  

28

 

AD[22]

  

GND

  

AD[20]

  

AD[21]

  

29

 

  

30

 

GND

  

AD[19]

  

AD[18]

  

+3.3V

  

31

 

  

32

 

AD[16]

  

AD[17]

  

+3.3V

  

C/BE[2]#

  

33

 

  

34

 

FRAME#

  

GND

  

GND

  

IRDY#

  

35

 

  

36

 

TRDY#

  

+3.3V

  

GND

  

DEVSEL#

  

37

 

  

38

 

STOP#

  

GND

  

+3.3V

  

LOCK#

  

39

 

  

40

 

Reserved

  

PERR#

  

Reserved

  

+3.3V

  

41

 

  

42

 

GND

  

SERR#

  

PAR

  

+3.3V

  

43

 

  

44

 

AD[15]

  

C/BE[1]#

  

+3.3V

  

AD[14]

  

45

 

  

46

 

AD[13]

  

GND

  

AD[11]

  

AD[12]

  

47

 

  

48

 

GND

  

AD[10]

  

AD[09]

  

M66EN

  

49

 

  

50

 

GND

  

GND

  

Connector

 

Key

 

Connector

 

Key

 

51

 

  

52

 

C/BE[0]#

  

AD[08]

  

+3.3V

  

AD[07]

  

53

 

  

54

 

AD[06]

  

+3.3V

  

AD[04]

  

AD[05]

  

55

 

  

56

 

GND

  

AD[03]

  

 

AD[02]

   

 

GND

   

 

57

   

  

 

58

   

 

AD[00]

   

 

AD[01]

   

 

V

 

(I/O)

   

 

V

 

(I/O)

   

 

59

   

  

 

60

   

 

REQ64#

  

 

ACK64#

   

 

+5V

   

 

+5V

   

 

61

   

  

 

62

   

 

+5V

   

 

+5V

   

Содержание Multi Port E1

Страница 1: ...One Stop Systems Inc OSS wanPCI CxT1E1 User Manual Rev A Multi Port T1 E1 J1 PCI Adapter OSS wanPCI CxT1E1...

Страница 2: ...upport is available for T1 E1 or J1 The OSS wanPCI CxT1E1 can use both SS7 or HDLC protocols Initial Set Up Unpacking Instructions 1 If the carton is damaged when you receive it request that the carri...

Страница 3: ...on between the RJ 48 jack on the adapter and the RJ 48 jack in your wall or test system 5 Turn on power to the computer Adapter installation is complete 6 Reverse the above procedure to remove the boa...

Страница 4: ...or both T1 1 544MHz or E1 2 048MHz Logical channels can be mapped as any combination of DS0 time slots to support ISDN hyperchannels Nx64Kbps or as any number of bits in a DS0 for subchanneling applic...

Страница 5: ...CI CxT1E1 supports four T1 E1 J1 ports Four PM4351 COMET chip sets provide the framer and LIU to support the four T1 E1 J1 ports The CSU components reside on the OSS wanPCI CxT1E1 The tip and ring for...

Страница 6: ...AD 30 AD 31 3 3V AD 29 21 22 AD 28 GND AD 26 AD 27 23 24 GND AD 25 AD 24 3 3V 25 26 IDSEL C BE 3 3 3V AD 23 27 28 AD 22 GND AD 20 AD 21 29 30 GND AD 19 AD 18 3 3V 31 32 AD 16 AD 17 3 3V C BE 2 33 34...

Страница 7: ...rd serial numbers are stored in a Microchip 93LC46A and packaged in a small outline integrated circuit This device can hold 1024 bits organized in a 128x8 format The PCI host reads and writes to this...

Страница 8: ...to be at zero 9 Periodically read the data in bit until a one is found 10 Write a byte with both the chip select and data out bits at zero 11 Disable EEPROM Reading from the EEPROM 1 Set the chip sele...

Страница 9: ...One Stop Systems Inc OSS wanPCI CxT1E1 User Manual Rev A 9 Clock Frame Pulse Routing Matrix continued...

Страница 10: ...up the access time and enables the EBus for individual accesses 4 Depending on how you want the board configured write to the MCLK register next to configure which ports are E1 and which are T1 Then...

Страница 11: ...t specific mode of operation Serial EEPROM A 500ns delay is necessary for both read and write cycles of the serial EEPROM Since the MUSYCC s data cycle time is approximately 300ns the algorithm by whi...

Страница 12: ...ck Select Register Any or all of the COMETs can provide the clock for data synchronization The host via the MCSR decides which COMET provides the clock At reset each COMET provides the clock for its p...

Страница 13: ...ort 1 1 COMET 1 MCLK E1 Port2 0 COMET 2 MCLK T1 Port2 1 COMET 2 MCLK E1 Port3 0 COMET 3 MCLK T1 Port 3 1 COMET 3 MCLK E1 Type 1 0 00 4 Ports Available 01 1 Ports Available 10 2 Ports Available Other v...

Страница 14: ...YCC transfers this interrupt from the EBus to the PCI INTB pin when enabled in the Global Configuration Descriptor The PCI host processor reads the interrupt register to determine which device was res...

Страница 15: ...in The board JTAG chain is not supported at the PCI connection The following is the JTAG chain order For 2 port and 1 port options on board 0 ohm resistors are used to bypass the appropriate COMETs No...

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