One Stop Systems, Inc. OSS-wanPCI-CxT1E1 User Manual
Rev. A
10
Initialization
The OSS-wanPCI-CxT1E1 must be reset and initialized before it can be programmed. This section contains the necessary code to
reset and initialize the waveform and the equalizer registers
.
Reset Functions
After powerup, a Dallas DS1817 chip generates a reset that forces all components on the OSS-wanPCI-CxT1E1 into a reset state
that terminates after 150ms. A second reset source is the PMC’s #RST pin from the PCI or VME host.
The host must configure the MUSYCC as a PCI master; this allows the MUSYCC to access host memory addresses. The host also
must write to the function 1 PCI configuration command register, enabling access to the OSS-wanPMC-CxT1E1EBus space
.
The following steps outline the sequence of events to bring up the board after a reset condition
.
1. Map function 0 and function 1 into the PCI’s memory address space. Each function requires at least 1 megabyte of
memory space.
2. Enable memory accesses onto the PMC’s space.
3. Write to the Global Configuration Descriptor in the MUSYCC that sets up the access time and enables the EBus for
individual accesses.
4. Depending on how you want the board configured, write to the MCLK register next to configure which ports are E1 and
which are T1. Then write to the master clock select register (MCSR) to define which port(s) should be master.
5. Initialize the COMETs based on the MCSR setting.
6. Initialize the MUSYCC to support your specific requirements.
COMET and MUSYCC Initialization
The COMETs and the MUSYCC must be initialized so that the data being clocked in and out of the MUSYCC occurs on the proper
edges. The following settings serve both master and slave clock modes in the COMET. These lines of code initialize the clock edge
to strobe data out of the MUSYCC, out of the COMET, and on the receive side as well.
COMET configuration for the powerup default settings of the MCLK and MCS registers as master
Register 0x30; BRIF Configuration
NXDSO[1-0] = 0
CMODE = 0 BRCLK as an output
DE = 0: Use the falling edge of BRCLK
FE = 0: Use falling edge of BRCLK
Register 0x31; BRIF Frame Pulse Configuration
FPMODE = 0 BRFP as an output
Register 0x40; BTIF Configuration
NXDSO[1,0] = 0
CMODE = 1 BTCLK as an input
DE = 1: Use the rising edge of BTCLK
FE = 1: Use rising edge of BTCLK
Register 0x41; BTIF Frame Pulse Configuration
FPMODE = 1 BTFP as an input
