One Stop Systems, Inc. OSS-wanPCI-CxT1E1 User Manual
Rev. A
8
Enable EEPROM
1. Set the chip-select bit and write a one to the EEPROM (serial bit).
2. Keep the chip-select bit set and write the EWEN bit sequence. This includes the don’t care address bits.
3. Write the last byte with both the chip-select and data-out bits at zero.
Disable EEPROM
1. Set the chip-select bit and write a one to the EEPROM (serial bit).
2. Keep the chip-select bit set and write the EWDS bit sequence. This includes the don’t care address bits.
3. Write the last byte with both the chip-select and data-out bits at zero.
Writing to the EEPROM
1. Enable EEPROM.
2. Set the chip-select bit and write a one to the EEPROM.
3. Keep the chip-select bit set and write the WRITE bits in two writes to the EEPROM.
4. Keep the chip-select bit set and do seven writes indicating the address of interest.
5. Keep the chip-select bit set and do eight writes with the data byte to load. Start with the most significant bit, D7.
6. Write a byte with both the chip-select and data-out bits at zero.
7. Write a byte again with the chip-select bit set.
8. Do two reads of the EEPROM. Discard the first read and check the second read for the data-in bit to be at zero.
9. Periodically read the data-in bit until a one is found.
10. Write a byte with both the chip-select and data-out bits at zero.
11. Disable EEPROM.
Reading from the EEPROM
1. Set the chip-select bit and write a one to the EEPROM.
2. Keep the chip-select bit set and write the READ bits in two writes to the EEPROM.
3. Keep the chip-select bit set and do seven writes indicating the address of interest.
4. Keep the chip-select bit set and do nine reads. Discard the first read. The eight remaining reads take the data from the
data-in bit and shift it to the least significant bit position. Data is read starting from most significant bit position, D7.
(Remember the data-in bit is at position one.)
5. Write a byte with both the chip-select and data-out bits at zero.
Clock/Frame Pulse Routing Matrix
Any one of the framers can provide the clock for data synchronization. The host, via the MCSR (Master Clock Select Register) can
decide which framer provides the clock. After power-up or reset, the MCSR is reset and all framers synchronize to the clock input
provide by XCLK. XCLK is an input to the framers and its source is one of the two on board oscillators (T1 or E1) and controlled by
the MCLK register. Upon power up or reset, the MCLK register provides T1 clock to all framers. Thereafter, the host can manipulate
the MCLK register to provide T1 or E1 to any framer. See diagram next page
