One Stop Systems, Inc. OSS-wanPCI-CxT1E1 User Manual
Rev. A
11
COMET configuration for the slave setting
Register 0x30; BRIF Configuration
NXDSO[1,0] = 0
CMODE = 1 BRCLK as an input
DE = 0: Use the falling edge of BRCLK
FE = 0: Use falling edge of BRCLK
Register 0x31; BRIF Frame Pulse configuration
FPMODE = 1 BRFP as an input
Register 0x40; BTIF configuration
NXDSO[1,0] = 0
CMODE = 1 BTCLK as an input
DE = 1: Use the rising edge of BTCLK
FE = 1: Use rising edge of BTCLK
Register 0x41; BTIF Frame Pulse Configuration
FPMODE = 1 BTFP as an input
Note
: NXDSO[1,0] This is the recommended setting, full frame. For other configurations, we recommend configuring the MUSYCC
for that specific mode of operation
.
Serial EEPROM
A 500ns delay is necessary for both read and write cycles of the serial EEPROM. Since the MUSYCC’s data cycle time is
approximately 300ns, the algorithm by which data is read from the serial EEPROM in a timely fashion will be as follows
:
•
The EEPROM must go through an EEPROM enable command at least once and is not disabled until the operation is
complete. Only PCI single writes and reads can be used.
•
A minimum of 500ns delay must exist between each single host access to and from the serial EEPROM.
Global configuration descriptor
BLAPSE[2-0] = 7
ECKEN = 1
Enable PCI clock to the EBUS
MPUSEL = 0
ALAPSE[1-0] = 3
ELAPSE[2-0] = 7
PORTMAP[1-0] = 0
Port configuration descriptor
ROOF_EDGE = 0
It is not used on this product
RSYNC_EDGE = 1
Rising edge
RDAT_EDGE = 1
Rising edge
TSYNC_EDGE = 1
Rising edge
TDAT_EDGE = 0 Falling
edge
