One Stop Systems, Inc. OSS-wanPCI-CxT1E1 User Manual
Rev. A
14
LED register
There are ten LEDs mounted on the front panel connectors. Eight LEDs are programmable and can be used for AIS and RAI
alarms. The ninth LED is the power LED (see Section 6-2). The tenth LED is the power LED The table below defines each bit in the
LED register
0 = OFF
1 = ON
Interrupts
The MUSYCC requires the use of PCI signals INTA# and INTB#.
•
INTA# is driven by the MUSYCC to indicate a MUSYCC layer-2 interrupt condition to the PCI host processor.
•
INTB# is driven by the MUSYCC to notify the PCI host processor of an interrupt pending from the EBus. Interrupts from the
COMETs are latched in a register resident in the iSPLD. The interrupts from the COMETs are logically OR-ed to generate
an interrupt to the MUSYCC. The MUSYCC transfers this interrupt from the EBus to the PCI INTB# pin when enabled in
the Global Configuration Descriptor. The PCI host processor reads the interrupt register to determine which device was
responsible for the interrupt. These bits are direct links from each COMET. They are cleared only when that COMET.s
interrupts have been cleared
0 = No interrupt
1 = Interrupt pending
X = Reserved (don.t care)
The appropriate COMET clears the interrupt bit when the interrupt is serviced
Power LED
The ninth LED is the power LED. This bicolor LED indicates the status of the 2.5V regulator. The power LED is not software
accessible
.
Power LED
Bicolor
2.5 Volt
Status
Green
Power is OK
Red
Power is BAD
LED Register – 0xD0002 Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CR8
Yellow
CR9
Green
CR6
Yellow
CR7
Green
CR4
Yellow
CR5
Green
CR2
Yellow
CR3
Green
Interrupt Register – Address Offset = 3 – Read Only
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
COMET 4
COMET 3
COMET 2
COMET 1
