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One Stop Systems, Inc.                                                                                                          OSS-wanPCI-CxT1E1 User Manual  

Rev. A    

   

                                 12 

In-System Programmable Logic Device (iSPLD)  

The In-System Programmable Logic Device (iSPLD) contains all of the necessary logic required by the CN8474A to communicate 

with its peripheral components. The iSPLD serves two purposes

:  

 

1.  As a general logic device, supplying correct signal timing and address decoding for chip selects to the COMETs and 

EEPROM.  

2.  To provide registers to control the crystal routing and BRCLK routes to and from the COMETs and MUSYCC.  

 

The iSPLD is an Altera EPM3256AE and serves the following logic functions:  

 

• 

T1/E1/J1 clock routing to all COMETs  

• 

COMET interrupts  

• 

Serial EEPROM control  

• 

COMET control  

• 

LED control  

• 

Master clock connections  

• 

Reset functions  

iSPLD registers, base address (EAD) = 0xD0000 

 

 

 

 

 

 

 

iSPLD Control 

Functions  

Write/read operations executed by the CN8474A via its EBus are translated to the appropriate timing for the PMC4351. The iSPLD 

decodes the address and generates the chip-select levels for each of the COMETs 

 

Master Clock Select Register

  

Any or all of the COMETs can provide the clock for data synchronization. The host, via the MCSR, decides which COMET provides 

the clock. At reset, each COMET provides the clock for its port and must be configured as the master. In modes other than default 

or reset, one port is assigned the master with the iSPLD routing this clock to the remaining COMETs and MUSYCC.  

 

The MCSR in the iSPLD can be written to and read by the PCI host. Immediately after powerup or host reset this register is 

initialized to all zeros. By default, COMET 1 serves to provide the master clock. The host may then select the clocking needs via the 

MCSR. See Master Clock Registers Table on next page for information about the MCSR and clocking information. 

 

The MCSR in the CPLD is a read/write register combined with the Board ID Register (BIDR), a read-only register. The power-up 

default value of this register is 10 Hex

.

 

 

BIDR Register – Address = 0xD0000 

MCSR Register – Address = 0xD0000 

Read Only 

Read/Write 

Bit 7  

Bit 6  

Bit 5  

Bit 4  

Bit 3  

Bit 2  

Bit 1  

Bit 0  

1  MCSR3  

MCSR2  

MCSR1  

MCSR0  

Address offset   Register type 

Function  

0x0  

Write/read  

MCSR  

0x4  

Write/read  

MCLK register  

0x8  

Write/read  

LED register  

0xC  

Read only  

Interrupt register 

Содержание Multi Port E1

Страница 1: ...One Stop Systems Inc OSS wanPCI CxT1E1 User Manual Rev A Multi Port T1 E1 J1 PCI Adapter OSS wanPCI CxT1E1...

Страница 2: ...upport is available for T1 E1 or J1 The OSS wanPCI CxT1E1 can use both SS7 or HDLC protocols Initial Set Up Unpacking Instructions 1 If the carton is damaged when you receive it request that the carri...

Страница 3: ...on between the RJ 48 jack on the adapter and the RJ 48 jack in your wall or test system 5 Turn on power to the computer Adapter installation is complete 6 Reverse the above procedure to remove the boa...

Страница 4: ...or both T1 1 544MHz or E1 2 048MHz Logical channels can be mapped as any combination of DS0 time slots to support ISDN hyperchannels Nx64Kbps or as any number of bits in a DS0 for subchanneling applic...

Страница 5: ...CI CxT1E1 supports four T1 E1 J1 ports Four PM4351 COMET chip sets provide the framer and LIU to support the four T1 E1 J1 ports The CSU components reside on the OSS wanPCI CxT1E1 The tip and ring for...

Страница 6: ...AD 30 AD 31 3 3V AD 29 21 22 AD 28 GND AD 26 AD 27 23 24 GND AD 25 AD 24 3 3V 25 26 IDSEL C BE 3 3 3V AD 23 27 28 AD 22 GND AD 20 AD 21 29 30 GND AD 19 AD 18 3 3V 31 32 AD 16 AD 17 3 3V C BE 2 33 34...

Страница 7: ...rd serial numbers are stored in a Microchip 93LC46A and packaged in a small outline integrated circuit This device can hold 1024 bits organized in a 128x8 format The PCI host reads and writes to this...

Страница 8: ...to be at zero 9 Periodically read the data in bit until a one is found 10 Write a byte with both the chip select and data out bits at zero 11 Disable EEPROM Reading from the EEPROM 1 Set the chip sele...

Страница 9: ...One Stop Systems Inc OSS wanPCI CxT1E1 User Manual Rev A 9 Clock Frame Pulse Routing Matrix continued...

Страница 10: ...up the access time and enables the EBus for individual accesses 4 Depending on how you want the board configured write to the MCLK register next to configure which ports are E1 and which are T1 Then...

Страница 11: ...t specific mode of operation Serial EEPROM A 500ns delay is necessary for both read and write cycles of the serial EEPROM Since the MUSYCC s data cycle time is approximately 300ns the algorithm by whi...

Страница 12: ...ck Select Register Any or all of the COMETs can provide the clock for data synchronization The host via the MCSR decides which COMET provides the clock At reset each COMET provides the clock for its p...

Страница 13: ...ort 1 1 COMET 1 MCLK E1 Port2 0 COMET 2 MCLK T1 Port2 1 COMET 2 MCLK E1 Port3 0 COMET 3 MCLK T1 Port 3 1 COMET 3 MCLK E1 Type 1 0 00 4 Ports Available 01 1 Ports Available 10 2 Ports Available Other v...

Страница 14: ...YCC transfers this interrupt from the EBus to the PCI INTB pin when enabled in the Global Configuration Descriptor The PCI host processor reads the interrupt register to determine which device was res...

Страница 15: ...in The board JTAG chain is not supported at the PCI connection The following is the JTAG chain order For 2 port and 1 port options on board 0 ohm resistors are used to bypass the appropriate COMETs No...

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