EVBUM2277/D
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9
Register 4: INTG_START Line
Short integration times may be controlled through use of
the Electronic Shutter. The default setting written to
Register 4 controls the line number on which the Electronic
Shutter will occur. The DIO[11..7] inputs are used to control
the Integration time, by selecting pre-programmed line
numbers, as shown in Table 14.
In Free-Running Mode, the Electronic Shutter pulse
occurs during the previous frame readout. The line number
values are chosen to allow integration times adjustable in
increments of one-eighth the Frame or Flush time.
If the line number is greater than the number of lines
specified in a Frame Table (Register 8), the Electronic
Shutter will not occur. This is the method used to turn the
Shutter off; in this case, the integration time is controlled by
a counter in the Altera PLD (See Table 25).
Table 14. REGISTER 4 DEFAULT SETTING
DIO[11..7]
Frame/Flush Integration
Free-Running Mode
Integrate Start Pulse Line Number[0..12]
0
1
2040 (Default – No Pulse)
1
1/8
966
2
1/4
828
3
3/8
690
4
1/2
552
5
5/8
414
6
3/4
276
7
7/8
138
> 7
See Table 25
2040 (No Pulse)
Register 5: Signal Polarity
The default settings written to Register 5 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 15. REGISTER 5 DEFAULT SETTING
Register Entry
1-channel
2-channel
Evaluation Board Signal Name
H6_IDLE_VAL
0
0
(Not Used)
H3_IDLE_VAL
1
1
H1A
H4_IDLE_VAL
0
0
H2A
H1_IDLE_VAL
1
0
H2B
H5_IDLE_VAL
0
0
(Not Used)
H2_IDLE_VAL
0
1
H1B
RG_IDLE_VAL
1
1
RESET
SH2_IDLE_VAL
1
1
SHP1
SH1_IDLE_VAL
1
1
SHP2
SH4_IDLE_VAL
1
1
SHD1
SH3_IDLE_VAL
1
1
SHD2
DATACLK1_IDLE_VAL
1
1
ADCLK (to AFEs)
DATACLK2_IDLE_VAL
0
0
DATACLK (to Framegrabber)
CLPOB_IDLE_VAL
1
1
CLPOB
CLPDM_IDLE_VAL
1
1
CLPDM
AMP_ENABLE_IDLE_VAL
0
0
AMP_ENABLE
FRAME_VALID_IDLE_VAL
0
0
FRAME_VALID
LINE_VALID_IDLE_VAL
0
0
LINE_VALID
INTEGRATE_START_IDLE_VAL
0
0
INTG_START/VES
V1_IDLE_VAL
0
0
V3RD
V2_IDLE_VAL
0
0
(Not Used)
