EVBUM2277/D
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7
Table 9. DEFAULT AD9845A AFE REGISTER PROGRAMMING
Register
Address
Description
Value
(decimal)
Notes
0
Operation
128
1
VGA Gain
(KAI−2093)
340
Corresponds to a VGA Stage Gain of 9.9 dB
2
Clamp
96
The Output of the AD9845A will be Clamped to Code 96 during the CLPOB Period
3
Control
8
CDS Gain Enabled
4, 5, 6, 7
PXGA Gain
43
Corresponds to a PXGA Stage Gain of 0.0 dB
KSC−1000 Timing Generator Default Settings
On power-up or board reset, The KSC−1000 is
programmed to the default settings as detailed in Table 10
through Table 24. See the KSC−1000 Device Specification
(
References
) for details of the KSC−1000 registers.
Register 0: Frame Table Pointer
Register 0 contains the Frame Table Pointer, which
instructs the KSC−1000 to perform the timing sequence
defined in that table. Frame Table 0 is used for Free-Running
Single Channel and Dual Channel modes, and Frame
Table 1 is used for Single Channel 2
×
2 Binning mode.
The default setting depends on the position of SW2.
Table 10. REGISTER 0 DEFAULT SETTING
Register Entry
Data (Normal Mode)
Data (Binning 2
y
2)
Frame Table Address
0
1
Register 1: General Setup
The default settings written to Register 1 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 11. REGISTER 1 DEFAULT SETTING
Register Entry
Data (1-channel)
Data (2-channel)
Pixels Per Line[0..12]
2016
1008
Line Valid Pixel Start[0..12]
9
9
Line Valid Pixel Quadrature Start[0..1]
0
0
Line Valid Pixel End[0..12]
2004
1007
CLPOB1_Pix_Start[0..12]
1982
1000
CLPOB1_Pix_End[0..12]
1992
1004
CLPOB2_Pix_Start[0..12]
0
0
CLPOB2_Pix_End[0..12]
0
0
CLPDM1_Pix_Start[0..12]
6
22
CLPDM1_Pix_End[0..12]
16
30
CLPDM2_Pix_Start[0..12]
0
0
CLPDM2_Pix_End[0..12]
0
0
PBLK_Pix_Start[0..12]
2002
1001
PBLK_Pix_End[0..12]
1
1
RG_Enable
1
1
H6_Enable
0
0
H4_Enable
1
1
H5_ Enable
0
0
SH2_Enable
1
1
SH4_Enable
1
1
