EVBUM2277/D
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6
Table 7. CCD TIMING
(continued)
Description
Notes
Pixel
Counts
Time
Symbol
VCCS Pedestal Time
T
3P
25.05
m
s
501
Photodiode Transfer Time
TV
3rd
12.30
m
s
246
V2 3
rd
Level
Photodiode Delay
T
3D
20.00
m
s
400
Photodiode Frame Delay
T
3FD
85.50
m
s
1710
Delay before 1
st
Line Transfer
Photodiode Transfer Period
T
3P
T
142.85
m
s
2857
T
3PT
= T
3P
+ T
V3rd
+ T
3D
+ T
3FD
Shutter Pulse Setup
T
EL
1.50
m
s
30
Shutter Pulse Time
T
S
10.0
m
s
200
Shutter Pulse Delay
T
SD
1.50
m
s
30
PCI−1424 Timing Conditions
Table 8. PCI−1424 TIMING
Description
Symbol
Time
Pixel
Counts
Notes
PIX Period
T
PIX
50.0 ns
1
20 MHz Clocking of DATACLK Sync Signal
FRAME Time
T
FRAME
127.2 ms
2,544,117
T
FRAME
= T
PIX
* ((V
period
+ H
PIX
) * V
PIX
+ T
3PT
)
MODES OF OPERATION
The following modes of operation are available to the
user:
Electronic Shutter Modes
The Evaluation Board electronic shutter circuitry
provides a method of precisely controlling the image
exposure time without any mechanical components. Charge
may be cleared from the CCD photodiodes at some time
during the readout of the previous frame. This allows
integration times of less than one frame time, to compensate
for high light exposures that would otherwise saturate the
CCD.
In Free-Running Mode, the default integration time can be
set from 1
×
to 1/8
×
frame time via the digital inputs
DIO[11..7] (See Table 14 and Table 25). When changing the
integration time, the user must initiate a Board Reset for the
change to take effect, either by pressing the
BOARD_RESET button (S1) on the Timing Board, or by
setting and resetting the Remote Reset (DIO14) input.
Black Clamp Mode
One of the features of the AD9845A AFE chip is an
optical black clamp. The black clamp (CLPOB) is asserted
during the CCD’s dark pixels and is used to remove residual
offsets in the signal chain, and to track low frequency
variations in the CCD’s black level. The location of these
pulses is fixed in the default KSC−1000 settings, but can be
adjusted dynamically through the 3-wire serial interface.
The default settings are shown in Table 11.
POWER-ON/BOARD RESET INITIALIZATION
When the board is powered up, the Board Reset button is
pressed, or the Remote Rest (DIO14) is toggled, the Altera
PLD is internally reset. When this occurs, state machines in
the PLD will first serially load the initial default values into
the AFE registers, then will load the KSC−1000 frame
tables, line tables, and registers.
Upon completion, the KSC−1000 will be ready to proceed
according to its programmed configuration. In the
background, the Altera PLD monitors the activity of the
3-wire Serial Interface, and monitors and interacts with the
KSC−1000.
AFE Register Default Settings
On power-up or board reset, the AFE registers are
programmed to the default levels shown in Table 9. See the
AD9845A specifications (
References
) for details of the
AFE registers.
