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3
Figure 3. KSC−1000 Initialization Timing
R/W
A0
A1
A2
A3
D0
D1
D2
SLOAD_TG
SDATA
SCLK
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[Dummy Bits]
The data for each KSC−1000 register is formatted into
bytes of data, as shown in Figure 3. The Read/Write bit is
always low, and the Address bits specify the register being
programmed, as shown in Table 3. Each byte is read into an
8-bit shift register, and is shifted out of the PLD as a serial
stream of eight bits. The last byte of data sent to a particular
register may need to be padded with extra “dummy” bits;
the SLOAD_TG signal is brought HIGH at the appropriate
time so that the correct number of bits are streamed into each
register, and the extra bits are ignored. Each register in the
KSC−1000 is programmed in this fashion until the entire
device is programmed.
Table 3. KSC−1000 REGISTERS
Register Address
Register Description
Data Bits
0
Frame Table Pointer
3
1
General Setup
202
2
General Control
2
3
INTG_STRT Setup
30
4
INTG_STRT Line
13
5
Signal Polarity
25
6
Offset
78
7
Width
65
8
Frame Table Access
(Variable)
9
Line Table Access
(Variable)
PLD State Machine
The Altera PLD contains a State Machine that parallels
the operation of the KSC−1000. The PLD controls the
KSC−1000 through the VD_TG output, and monitors
several of the KSC−1000 outputs, enabling it to track and
control the operation of the Timing Generator.
Remote Board Reset
The DIO14 input is used as a remote Board Reset control
line. The Altera PLD monitors this input, and when DIO14
goes HIGH, the ARSTZ (active low) output to the
KSC−1000 is asserted, disabling and clearing the timing
generator. When DIO14 goes LOW, the ARSTZ output is
de-asserted, and the Power-up/Board Reset initialization
sequence is executed. This allows programmable control of
the timing sequences to change the Electronic Shutter
position, for example.
Integration Clock
The Altera PLD uses the System Clock and an internal
counter to generate a 1.0 ms-period clock. This clock is used
to generate an internal delay after power-up or Board Reset.
It may also be used to control precise integration times for
the image sensor.
Output Channel Control
PLD input SW0 is used to select one of the supported
operation modes: Full Field Single Output, and Full Field
Dual Output. When making a change to the switch settings,
the user must initiate a Board Reset for the change to take
