ON Semiconductor KAI-2093, Руководство пользователя

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5
Outputs
The Altera PLD outputs include: the 3-wire serial
interface; control signals to the KSC−1000;
the INTEGRATE signal used for external monitoring and
synchronization; the PLD[2..0] signals which are auxiliary
Imager Board control bits; and the GIO[2..0] bits which are
used for PLD monitoring and testing.
Table 5. ALTERA OUTPUTS
Symbol Description
PLD_OUT0 KAI−2093 Video MUX Control
PLD_OUT1 (Not Used for KAI−2093 Operation)
PLD_OUT2 (Not Used for KAI−2093 Operation)
GIO[2..0] (Not Used for KAI−2093 Operation)
SLOAD_AFE_1 Serial Load Enable, Ch1 AD9845A AFE
SLOAD_AFE_2 Serial Load Enable, Ch2 AD9845A AFE
SLOAD_TG Serial Load Enable, KSC−1000
SDATA 3-wire Serial Interface DATA Signal Output
SCLOCK 3-wire Serial Interface CLOCK Signal Output
INTEGRATE High During CCD Integration Time
HD_TG (Not Used for KAI−2093 Operation)
VD_TG Control Signal to KSC−1000
ARSTZ Asynchronous Reset to KSC−1000 (from DIO14)
KAI−2093 TIMING CONDITIONS
System Timing Conditions
Table 6. SYSTEM TIMING
Description Symbol Time Notes
System Clock Period T
sys
25.0 ns 40 MHz System Clock
Unit Integration Time U
int
1.0 ms Generated by PLD
Power Stable Delay T
pwr
100 ms Typical
Default Serial Load Time T
sload
2.06 ms Typical
Integration Time T
int
Operating Mode Dependent
CCD Timing Conditions
Table 7. CCD TIMING
Description Symbol Time
Pixel
Counts
Notes
H1, H2, RESET Period T
pix
50.0 ns 1 20 MHz Clocking of H1, H2, RESET
VCCD Delay T
VD
50.0 ns 1 Delay after Hclks Stop
VCCD Transfer Time T
VCCD
1.75
m
s 35 V2 Rising Edge to V2 Falling Edge
HCCD Delay T
HD
1.55
m
s 31 Delay before Hclks Resume
Vertical Transfer Period V
period
3.35
m
s 67 V
period
= T
VD
+ T
VCCD
+T
HD
Horizontal Pixels H
PIX
100.80
m
s 2016 1992 CCD 24 Overclock Pixels
Vertical Pixels V
PIX
1220 1214 CCD Lines + 6 Overclock Lines
Line Transfer Time T
L
104.15
m
s 2083 TL = V HPIX