EVBUM2277/D
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18
Figure 12. Electronic Shutter Timing
Reg3 Entry
V1_CCD
V2_CCD
setup
width
hold
(Line Table 0)
30
200
30
Pix Counts
(not to scale)
VSUB
H1A_CCD
H2A_CCD
Start of Integration
Horizontal Timing
Figure 13 depicts the basic theoretical relationship
between the pixel-rate clocks to the CCD, the Video output
of the CCD, and the pixel-rate clocks to the AFE.
Figure 13. Horizontal Timing
VOUT_CCD
RESET_CCD
H2A_CCD
H1A_CCD
SHP
DATACLK
SHD
Tr
Tpix
Vpix
Vsat
Tshp
Tshd
Binning Mode Horizontal Timing
In order to sum the charge from two Horizontal CCD
pixels into one, the Reset clock is suspended on alternating
Horizontal clock cycles. In this way, two pixels of charge are
dumped onto the floating diffusion of the output amplifier
before this node is reset to VRD, the Reset Drain voltage.
See the KAI−2093 Device Specification (
References
) for
further details.
In order to correctly convert the output amplifier voltage
to digital data, the AFE clocks must be adjusted accordingly.
The Clamp pulse (SHP) samples the output after the Reset
pulse has been issued, but before the Horizontal clocks have
moved charge onto the floating diffusion. The Sample pulse
(SHD) samples the output after two Horizontal clock cycles
have moved two charge packets onto the floating diffusion.
The DATACLK then clocks the AFE to perform the
conversion.
The KSC−1000 has the capability of implementing the
Horizontal Timing necessary to bin up to four pixels. This
feature is controlled by setting bits 3:4 of the active Frame
Table (Register 8) in the KSC−1000. Figure 14 depicts the
basic theoretical relationship between the pixel-rate clocks
to the CCD, the Video output of the CCD, and the pixel-rate
clocks to the AFE in 2
×
Horizontal Binning Mode.
