EVBUM2277/D
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10
Table 15. REGISTER 5 DEFAULT SETTING
(continued)
Register Entry
Evaluation Board Signal Name
2-channel
1-channel
V3_IDLE_VAL
0
0
V2
V4_IDLE_VAL
1
1
V1
V5_IDLE_VAL
0
0
(Not Used)
V6_IDLE_VAL
0
0
FDG
Register 6: Pixel-Rate Signal Offset
The default settings written to Register 6 depend on the
position of SW0 on the Timing Board, used to select
between 1-channel and 2-channel operation.
Table 16. REGISTER 6 DEFAULT SETTING
Register Entry
Data
(1-channel)
Data
(2-channel)
CCD Signal Name
H6_OFFSET[0..5]
0
0
(Not Used)
H3_OFFSET[0..5]
32
32
H1A
H4_OFFSET[0..5]
29
29
H2A
H1_OFFSET[0..5]
33
31
H2B
H5_OFFSET[0..5]
0
0
(Not Used)
H2_OFFSET[0..5]
31
33
H1B
RG_OFFSET[0..5]
0
0
RESET
SH2_OFFSET[0..5]
31
31
SHP1
SH1_OFFSET[0..5]
31
31
SHP2
SH4_OFFSET[0..5]
63
63
SHD1
SH3_OFFSET[0..5]
63
63
SHD2
DATACLK1_OFFSET[0..5]
42
42
ADCLK (to AFEs)
DATACLK2_OFFSET[0..5]
0
0
DATACLK (to Framegrabber)
Register 7: Pixel-Rate Signal Width
The default settings written to Register 7 depend on the
position of SW0 on the Timing Board, used to select
between 1-Channel and 2-Channel operation.
Table 17. REGISTER 7 DEFAULT SETTING
Register Entry
Data
(1-channel)
Data
(2-channel)
CCD Signal Name
H6_WIDTH[0..4]
16
16
(Not Used)
H3_WIDTH[0..4]
13
13
H1A
H4_WIDTH[0..4]
18
18
H2A
H1_WIDTH[0..4]
13
18
H2B
H5_WIDTH[0..4]
16
16
(Not Used)
H2_WIDTH[0..4]
18
14
H1B
RG_WIDTH[0..4]
8
8
RESET
SH2_WIDTH[0..4]
14
14
SHP1
SH1_WIDTH[0..4]
14
14
SHP2
SH4_WIDTH[0..4]
14
14
SHD1
SH3_WIDTH[0..4]
14
14
SHD2
DATACLK1_WIDTH[0..4]
31
31
ADCLK (to AFEs)
DATACLK2_WIDTH[0..4]
16
16
DATACLK (to Framegrabber)
