Novametrix Medical Systems MARS PO2 TECH 2001, Руководство по обслуживанию

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Section 4
Theory of Operation 2776 DSP Module
24
Model 2001 Service Manual Rev. 01
select), serial data clocks (BCLKR0 & BCLKX0), and interrupt INT0. Since the UART is a 3.3V
device communicating to a 5V host, IC8 is necessary to provide level shifting from 5V down to
3.3V. Going in the opposite direction (3.3V to 5V) level shifting is not required (but is provided)
because the logic input thresholds for the 5V devices are satisfied by the 3.3V device output
levels. The UART also provides a CTS input and a RTS output which are brought over to J2
through IC8 however, they are not used in this design. The system reset signal (RESET) is
connected to IC8 (quad buffer) as an enable and RESET* is connected to the UART as a
shutdown.
DSP Processor
See sheet 1 of 2 on schematic.
A Texas Instruments (TMS320VC5410) digital signal processor (DSP) is the heart of the MARS
oximeter. It receives the 20 bit red and infrared channel data from the host processor
(HD64180) serially and calculates the saturation using two specialized algorithms. Upon power
up the DSP comes out of reset running at the system clock frequency of 6.144MHz as
generated by oscillator Y1 and configured by resistors R8, R12, and R14. The DSP then boots
from internal ROM where it sets itself up to continue booting up from external flash ROM IC2.
Once the program has been completely loaded into the DSP the external bus is shut down and
the internal clock is increased to 92.16 MHz by the internal PLL and the DSP runs completely
in internal memory. The DSP then runs at this frequency (internally) to satisfy the requirements
of it’s math intensive calculations. Once the DSP is up and running it starts the watchdog timer
output (XF) and transitions this output once every second. This output is also used as a status
indicator by turning Q1 on and off which illuminates D1 at a steady rate of .5Hz. If the watchdog
fails to transition due to either a hardware or software fault, a reset will be generated by IC5. If
for any reason this fails to bring the DSP back on line a complete system reset will be generated
by the host processor (SRSTIN*) and the DSP module will reboot.
Memory and Programmable Logic Device (PLD)
The DSP system software resides in IC2, a 512k x 8 (4 mega-bit) flash memory. IC2 connects
to the DSPs address and data bus with it’s control signals read (RD*), write (WR*), and enable
(ROMCS*) being decoded by IC3 which is a programmable logic device PLD. This device takes
the place of the discrete gates that could have been used and condenses it into one device. In
addition to decoding the previously mentioned signals, it also insures that the flash memory
cannot be over written during reset conditions and it also level shifts the host reset signal
(SRSTIN*) from 5V to 3.3V where it is a master reset input (SRSTOUT*) to the microprocessor
supervisor (IC5). At present, the flash memory is disabled from being written to by R18 which
bootstraps its write enable pin high.
JTAG Emulation Interface
The DSP module provides a JTAG emulation interface through J1. This interface is used during
development and therefore the header is not populated on the production modules.