Novametrix Medical Systems MARS PO2 TECH 2001, Руководство по обслуживанию

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2775 Main Board
Section 4
Theory of Operation
Rev. 01 Model 2001 Service Manual
21
TML-Two Minute LED drives the LED on the front display.
AOL-Audio Out LED drives the LED on the front panel.
ARL-Alert LED drives the LED on the front panel.
KJL*-drives Q17 when high which in turn drives the Alert Bar LEDs via J105.
BTL-Battery Low LED on the front panel.
DSPBR-(not used on the 2001)
OFFDIS-sent to the Power On/Off section of the circuitry to prevent the monitor from being
turned off while writing to RAM.
Watchdog Timer
See sheet 1 of 4 on schematic.
The Watchdog Timer provides a system reset function in the event a hardware or software
“glitch” occurs. The PEEL IC18 forms the heart of the Watchdog circuit.
At power up and at specific intervals thereafter, the microprocessor outputs a logic high to IC18
pin 8, WDOG (Watchdog). The WDOG signal combines with other signals within the PEEL and
as a result the Watchdog Clear (WDCLR) open drain output at IC18 pin 12 is continually
brought low. This discharges the capacitor C46 before it can charge up (via RP2 pins 1 and 2)
past the input threshold of IC21 pin 9.
If the WDOG pulse does not appear at regular intervals, as the result of a software or hardware
problem, the RC charges up and IC21 pin 8 goes low producing a Watchdog Time-out (WDTO*)
input at IC18 pin 11. WDTO* combines with other signals within the PEEL and causes the open
drain Master Reset (MR) output at IC18 pin 13 to be brought low.
A low MR causes C45 to discharge, forcing IC21 pin6 high. This sends a reset pulse to the
system. It also sets the Reset Input (RESIN) signal at IC18 pin 9 high which causes RESET* at
IC18 pin 19 to activate low. The active RESET line causes the microprocessor (IC16 pin 7) and
the display module to be reset. The monitor then performs its power up self-test routines, and
if the “glitch” has been cleared, the monitor resumes normal operation. If the problem still exists,
a self-test or other error should be displayed.
Serial I/O Controller
See sheet 1 of 4 on schematic.
Digital data from the three Analog-To-Digital Converters is read by the CPU through its clocked
serial data input (RXS) at IC16 pin 52. The PEEL IC18 acts as the Clocked Serial I/O (CSI/O)
Controller.
Except during power up or Watchdog Timer reset, IC39 pin 3 provides an interrupt to the CSI/
O controller in the form of a 5 millisecond period square-wave input to IC18 pin 7 (INT5MS).
On the rising edge of INT5MS, a CPU interrupt request is generated by IC18 pin 18 (CPUINIT*)
going low. The CPU responds by sending the clock input to CSI/O controller (CKS) at IC18 pin
6 low. (This CKS line is inactive high unless a serial receive operation is in progress.) The CPU
also sets up the ADC decode lines AA1 and AA0 at IC18 pins 5 and 4, and as a result, one of
the ADC chip select lines (CSADC1*, CSADC2*, CSADC3*) is brought low, and the CPUINIT*
line is disabled.