Novametrix Medical Systems MARS PO2 TECH 2001, Руководство по обслуживанию

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Section 4
Theory of Operation 2775 Main Board
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Model 2001 Service Manual Rev. 01
latch at IC14 pin 8 so that the CPU can detect if the unit is operating on AC line power (IC14
pin 8 high) or on battery power (IC14 pin 8 low). Diode D9 keeps current from back feeding into
IC14 when the monitor is turned off but still connected to the AC line.
The 2MIN (D3), AUDIO OFF (D4), ALERT (D5), and LOW BAT (D1) LEDs are driven by the 8-
bit latch IC13. When each of the corresponding signals is driven high the appropriate LED on
the keypanel is illuminated.
Display Interface
See sheet 1 of 4 on schematic.
The display is connected to the 2775 Main Board at J107. It is controlled by the processor using
the RD* (Read), WR* (Write), and DISPCS* (Display Chip Select) lines. Data bits D0-D7 are
used as input/output lines and A0 is used in conjunction with the RD* and WR* lines to
distinguish between read and write operations as listed below.
Table 1. Display Command/Data table.
See sheet 3 of 4 on schematic.
The CNTRST (Contrast) line is controlled by pressing the front panel key. When depressed and
held the processor controls the digital to analog converter IC29, line A0 is brought low along
with WR* and DACCS*, the data on D0-D7 controls the voltage at IC30 pin 7 which can vary
from 0-4 volts. The output of IC30 pin 7, along with 4VREF feeds a summing amplifier (IC30
pins 1, 2, 3). The output of the summing amplifier IC30 pin 3 controls the base of Q10 which in
turn controls the contrast of the display through a variable negative voltage.
The backlight for the display is controlled by the DSPBR (Display Bright) line. When DSPBR is
high the gate of Q16 is biased off, current flows from Vcc through R51 to IC45. This sets the
backlight for low illumination. The illumination of the backlight is made greater when DSPBR is
made low, this biases Q16 on which essentially shorts out R51 allowing more current to flow
into IC45 increasing the intensity of the backlight.
I/O Device Controller
See sheet 1 of 4 on schematic.
The A/D Converter Chip Selects, serial A/D Chip Selects, Sensor Status Decoding and NEXT*
line are all controlled by IC28 when selected by the OPORT line (IC21 pin 10). The OPORT line
will go high when the L1* and WR* line both go low at IC23 pins 13 and 12, this will send output
pin IC23 pin 11 low which drives inverter IC21 pin 10 high enabling IC28.
A 3 to 8 decoder is used to control the DACCS*, RTC*, DISPC*, AUD*, KEY*, L1*, L2*, 2KEYS*
lines. when the IOE* line goes low and the LIR* line goes high being inverted by IC21 pin 2 and
presented to IC22 pin 5 as a low enable line IC22 is enabled, Q0-Q7 will be driven low
depending upon the A4, A5 and A6 lines on pins 1, 2, 3 respectively on IC22.
With the LPORT line high IC13 is enabled, this latches the data on lines D0-D7 (1D-8D pins 2-
9) on its output pins 19-12 (1Q-8Q respectively), the outputs correspond to the following eight
lines:
CAL-used by the A/D Converters on power up to compensate for front end voltage offsets.
A0 RD* (active low) WR* (active low)
High Status Read Command Write
Low Data Read Data Write