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CHAPTER 14 SERIAL INTERFACE (SIO1)
Preliminary User’s Manual U13420EJ2V0UM00
SI1
SCK1
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF1
Transfer start at the falling edge of SCK1
End of transfer
SIO1 Write
SCL101 SCL100
Selects serial clock of serial interface (SIO1)
0
0
External clock input to SCK1 pin
Note 2
0
1
f
X
/2
3
(1.05 MHz)
1
0
f
X
/2
4
(524 kHz)
1
1
f
X
/2
5
(262 kHz)
Notes 1. When CSIE10 = 0 (SIO1 operation stop status), P84/SI1, P83/SO1, P82/SCK1, P81/BUSY, and
P80/STB pins can be used as port pins.
2. When external clock input is selected by clearing SCL101 and SCL100 to 0, 0, clear bits 2 (STRB0)
and 1 (BUSY10) of the automatic data transmit/receive control register (ADTC0) to 0,0.
Caution
Be sure to set bits 2 and 3 to 0.
(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. 1-bit unit data transmission/
reception is carried out in synchronization with the serial clock.
Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock (SCK1).
The transit data is held in the SO1 latch and is output from the SO1 pin. The receive data input to the SI1
pin is latched into SIO1 at the rising edge of SCK1.
Upon termination of 8-bit transfer, the SIO1 operation stops automatically and the interrupt request flag
(CSIIF1) is set.
Figure 14-5. 3-Wire Serial I/O Mode Timings
Caution
SIO1 pin becomes low level by SIO1 write.
Содержание mPD780065 Series
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