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CHAPTER 7 8-BIT TIMER/EVENT COUNTER
Preliminary User’s Manual U13420EJ2V0UM00
(2) Operated by CR5n transition
Figure 7-11. Timing of Operation by Change of CR5n
(a) CR5n value transits from N to M before overflow of TM5n
(b) CR5n value transits from N to M after overflow of TM5n
(c) CR5n value transits from N to M between two clocks (00H and 01H) after overflow of TM5n
n = 0, 1
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
CR5n transition (N
→
M)
N N+1 N+2
FFH 00H 01H
M M+1 M+2
FFH 00H 01H 02H
M M+1 M+2
N
02H
M
H
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
N
N+1 N+2
FFH 00H 01H
N
N+1 N+2
FFH 00H 01H 02H
N
02H
N
H
03H
M
M M+1 M+2
CR5n transition (N
→
M)
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
N
N+1 N+2
FFH 00H 01H
N
N+1 N+2
FFH 00H 01H 02H
N
02H
N
H
M
M M+1 M+2
CR5n transition (N
→
M)
Содержание mPD780065 Series
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